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1 v59c1512(404/804/164)qb high performance 512 mbit ddr2 sdram 4 banks x 32mbit x 4 (404) 4 banks x 16mbit x 8 (804) 4 banks x 8mbit x 16 (164) preliminary v59c1512(404/804/164)qb rev.1.3 november 2006 5 37 3 25a 25 ddr2-400 ddr2-533 ddr2-667 ddr2-800 ddr2-800 clock cycle time (t ck3 ) 5ns 5ns 5ns 5ns 5ns clock cycle time (t ck4 ) 5ns 3.75ns 3.75ns 3.75ns 3.75ns clock cycle time (t ck5 ) 5ns 3.75ns 3ns 3ns 2.5ns clock cycle time (t ck6 ) 5ns 3.75ns 3ns 2.5ns 2.5ns system frequency (f ck max ) 200 mhz 266 mhz 333 mhz 400 mhz 400 mhz features high speed data transfer rates with system frequency up to 400mhz posted cas programmable cas latency: 3, 4, 5 and 6 programmable additive latency:0, 1, 2, 3, 4 and 5 write latency=read latency-1 programmable wrap sequence: sequential or interleave programmable burst length: 4 and 8 automatic and controlled precharge command power down mode auto refresh and self refresh refresh interval: 7.8 us (8192 cycles/64 ms) ocd (off-chip driver impendance adjustment) odt (on-die termination) weak strength data-output driver option bidirectional differential data strobe (single-ended data-strobe is an optional feature) on-chip dll aligns dq and dqs transitions with ck transitions differential clock inputs ck and ck jedec power supply 1.8v 0.1v vddq=1.8v 0.1v available in 60-ball fbga for x4 and x8 component or 84 ball fbga for x16 component pasr partial array self refresh all inputs & outputs are compatible with sstl_18 in- terface tras lockout supported read data strobe supported (x8 only) internal four bank operations with single pulsed ras description the v59c1512(404/804/164)qb is a four bank ddr dram organized as 4 banks x 32mbit x 4 (404), 4 banks x 16mbit x 8 (804), or 4 banks x 8mbit x 16 (164). the v59c1512(404/804/164)qb achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. the chip is designed to comply with the following key ddr2 sdram features:(1) posted cas with additive la- tency, (2)write latency=read latency-1, (3)off-chip driv- er(ocd) impedance adjustment, (4) on die termination. all of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. i/o s are synchronized with a pair of bidirectional strobes (dqs, dqs ) in a source synchronous fashion. operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard drams. a se- quential and gapless data rate is possible depending on burst length, cas latency and speed grade of the device. available speed grade: -5 (ddr2-400) @ cl 3-3-3 -37 (ddr2-533) @ cl 4-4-4 -3 (ddr2-667) @ cl 5-5-5 -25a (ddr2-800) @ cl 6-6-6 -25 (ddr2-800) @ cl 5-5-5 device usage chart operating temperature range package outline ck cycle time (ns) power temperature mark 60 ball fbga 84 ball fbga -5 -37 -3 -25a -25 std. l 0c to 85c ? ????? ? ? blank
2 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb 123 4 5 678910 11 12 13 14 15 16 17 18 19 v 59 c 1 51280 4qb f 5 organization promos & refresh 64mx4, 8k : 25640 16mx16, 8k : 25616 32mx8, 8k : 25680 128mx4, 8k : 51240 32mx16, 8k : 51216 temperature 64mx8, 8k : 51280 blank: 0 - 85c type 256mx4, 8k : g0140 64mx16, 8k : g0116 i : -40 - 85c 59 : ddr2 cmos 128mx8, 8k : g0180 e : -40 - 125c speed 5 : 200mhz @cl3-3-3 voltage banks 37 : 266mhz @cl4-4-4 1 : 1.8 v 4 : 4 banks i/o 3 : 333mhz @cl5-5-5 8 : 8 banks q: sstl_18 rev level 25 : 400mhz @cl5-5-5 a: 1st c: 3rd 25a : 400mhz @cl6-6-6 b: 2nd d: 4th package rohs package special feature description l : low power grade f fbga u : ultra low power grade *rohs: restriction of hazardous substances 512mb addressing confi gura tion 128mb x 4 64mb x 8 32mb x1 6 # of bank 4 4 4 bank address ba0,ba1 ba0,ba1 ba0,ba1 auto precharge a 10 /ap a 10 /ap a 10 /ap row address a 0 ~ a 13 a 0 ~ a 13 a 0 ~ a 12 column address a 0 ~ a 9, a 11 a 0 ~ a 9 a 0 ~ a 9 ddr part number
3 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 x4 pack age pinout (top view) : 60ball fbga package notes: b1, b9, d1, d9 = nc for x4 organization. pins b3 has identical capacitance as pins b7. vddl and vssdl are power and ground for the dll. it is recommended that they are isolated on the device from vdd, vddq, vss, and vssq. a b c d e f g h j k l vdd nc vss nc vssq dm vddq vddq vddq vssq vssq dqs dqs nc dq0 vddq dq2 vssq nc vssdl vdd ck ras ck cas cs a2 a6 a4 a11 a8 nc a13 nc a12 a9 a7 a5 a0 vdd a10 vss vddq vssq dq1 dq3 nc vddl a1 a3 ba1 vref vss cke we ba0 1 2 3 7 8 9 vdd vss odt nc + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 123456789 a b c d e f g h j k l ball locations (x4) : populated ball + : depopulated ball top view (see the balls through the package)
4 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb notes: 1. pins b3 and a2 have identical capacitance as pins b7 and a8. 2. for a read, when enabled, strobe pair rdqs & rdqs are identical in function and timing to strobe pair dqs & dqs and input masking function is disabled. 3. the function of dm or rdqs/rdqs are enabled by emrs command. 4. vddl and vssdl are power and ground for the dll. it is recommended that they are isolated on the device from vdd, vddq, vss, and vssq. x8 package pinout (top view) : 60ball fbga package a b c d e f g h j k l vdd nu/ vss dq6 vssq vddq vddq vddq vssq vssq dqs dqs dq7 dq0 vddq dq2 vssq dq5 vssdl vdd ck ras ck cas cs a2 a6 a4 a11 a8 nc a13 nc a12 a9 a7 a5 a0 vdd a10 vss vddq vssq dq1 dq3 dq4 vddl a1 a3 ba1 vref vss cke we ba0 1 2 3 7 8 9 vdd vss dm/ rdqs rdqs nc odt + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 2 3 4 5 6 7 8 9 a b c d e f g h j k l + + ball locations (x8) : populated ball + : depopulated ball top v i ew (see the balls through the package)
5 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 a b c d e f g h j k l vdd nc vss ldq6 vssq ldm vddq vddq vddq vssq vssq l dqs ldqs ldq7 ldq0 vddq ldq2 vssq ldq5 vssdl vdd ck ras ck cas cs a2 a6 a4 a11 a8 nc nc nc a12 a9 a7 a5 a0 vdd a10 vss vddq vssq ldq1 ldq3 ldq4 vddl a1 a3 ba1 vref vss cke we ba0 1 2 3 7 8 9 vdd vss vdd nc vss udq6 vssq udm vddq vddq vssq udq1 udq3 udq4 vddq vddq vssq vssq u dqs udqs udq7 udq0 vddq udq2 vssq udq5 nc odt m n p r notes: vddl and vssdl are power and ground for the dll. lt is recommended that they are isolated on the device from vdd, vddq, vss, and vssq. x16 package pinou t (top view) : 84 ball fbga packa ge + + + + + + + + + + + 1 2 3 4 5 6 7 8 9 a b c d e f g h j k l + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + m n p r + + + + + + : populated ball + : depo pul ated ball top v i ew ball locations (x16) (see the balls through the package)
6 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb signal pin description pin type function ck ck input the system clock input. all inputs except dqs and dms are sampled on the rising edge of ck. cke input activates the ck signal when high and deactivates the ck signal when low, thereby initiates either the power down mode, or the self refresh mode. cs input cs enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras , cas we input when sampled at the positive rising edge of the clock, cas , ras , and we define the command to be executed by the sdram. a0 - a13 input during a bank activate command cycle, a0-a13 defines the row address (ra0-ra13) when sampled at the rising clock edge for x4 and x8 and a0-a12 row address for x16 device. during a read or write command cycle, a0-an defines the column address (ca0-can) when sampled at the rising clock edge.can depends on the sdram organization: 128m x 4 ddr can = ca9, a11 64m x 8 ddr can = ca9 32m x 16 ddr can = ca9 in addition to the column address, a10(=ap) is us ed to invoke autoprecharge operation at the end of the burst read or write cycle. if a10 is high, autoprecharge is selected and ba0, ba1 defines the bank to be precharged. if a10 is low, autoprecharge is disabled. during a precharge command cycle, a10(=ap) is used in conjunction with ba0 and ba1 to control which bank(s) to precharge. if a10 is high, a ll four banks will be precharged simultaneously regardless of state of ba0 and ba1. ba0, ba1 input selects which bank is to be active. dqx ldqx,udqx input/ output data input/output pins operate in the same manner as on conventional drams. dq0-dq3 for x4 component, dq0-dq7 for x8 component and ldq0-ldq7 , udq0-udq7 for x16 component. dqs,(dqs ) ldqs,(ldqs ) udqs,(udqs ) rdqs,(rdqs ) input/ output data strobe, output with read data, input with writ e data. edge-aligned with read data, centered in write data. for the x16 component, ldqs corresponds to the data on ldq0-ldq7; udqs coresponds to the data on udq0-udq7. for the x8, an rdqs option using dm pin can be enabled via the emrs(1) to simplify read timing. the data strobes dqs, ldqs, udqs, and rdqs may be used in single ended mode or paired with optional complimentary signals dqs , ldqs , udqs , and rdqs to provide differ- ential pair signaling to the system during both reads and writes. an emrs(1) control bit enables or dis- ables all complementary data strobe signals. in this data sheet, ?differential dqs signals? refers to any of the following with a10 = 0 of emrs(1) x4 dqs/dqs x8 dqs/dqs if emrs(1)[a11] = 0 x8 dqs/dqs , rdqs/rdqs if emrs(1)[a11] = 1 x16 ldqs/ldqs and udqs/udqs ?single-ended dqs signals? refers to any of the following with a10 = 1 of emrs(1) x4 dqs x8 dqs if emrs(1)[a11] = 0 x8 dqs, rdqs, if emrs(1)[a11] = 1 x16ldqs and udqs
7 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 dm, ldm,udm input in write mode, dm has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if is high for x 16 ldm corresponds to data on ldq0-ldq7, udm corresponds to data on udq0-udq7. vdd,vss supply power and ground for the input buffers and the core logic. vddq vssq supply isolated power supply and ground for the output buffers to provide improved noise immunity. 1.8v +/- 0.1v vref input sstl reference voltage for inputs vddlq vssdl supply isolated power supply and ground for the dll to provide improved noise immunity. 1.8v +/- 0.1v odt input on die termination enable. it enables termination resistance internal to the dram. odt is applied to each dq, dqs, dqs and dm signals for x4 component and dq, dqs, dqs , rdqs, rdqs and dm for the x8 component. for x16 configuration odt is applied to each dq, udqs/udqs , ldqs/ldqs , udm and ldm signal. odt will be ignored if emrs disable the function. rfu reserved for future use
8 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb self idle setting emrs bank precharging power writing act rda read srf ref ckel mrs ckeh ckeh ckel write automatic sequence command sequence rda wra read pr, pra pr refreshing refreshing down power down active with rda reading with wra active precharge reading writing pr(a) = precharge (all) mrs = (extended) mode register set srf = enter self refresh ref = refresh ckel = cke low, enter power down ckeh = cke high, exit power down, exit self refresh act = activate wr(a) = write (with autoprecharge) rd(a) = read (with autoprecharge) note: use caution with this diagram. it is indented to provide a floorplan of the possible state transitions simplified state diagram all banks precharged activating ckeh read write ckel mrs ckel sequence initialization ocd calibration ckel ckel ckel autoprecharge autoprecharge pr, pra pr, pra and the commands to control them, not all details. in particular situations involving more than one bank, enabling/disabling on-die termination, power down enty/exit - among other things - are not captured in full detail.
9 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 basic functionality read and write accesses to the ddr2 sdram are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coinci- dent with the active command are used to select the ba nk and row to be accessed (ba0, ba1 select the bank; a0-a13 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access and to determine if the auto precharge command is to be issued. prior to normal operation, the ddr2 sdram must be init ialized. the following sections provide detailed infor- mation covering device initialization, register de finition, command descriptions and device operation. power up and initialization ddr2 sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may resu lt in undefined operation. pow er-up and ini tialization seq uence the following sequence is required for power up and initialization. 1. apply power and attempt to maintain cke below 0.2*vddq and odt *1 at a low state (all other inputs may be undefined.) - vdd, vddl and vddq are driven from a single power converter output, and - vtt is limited to 0.95 v max, and - vref tracks vddq/2. or - apply vdd before or at the same time as vddl. - apply vddl before or at the same time as vddq. - apply vddq before or at the same time as vtt & vref. at least one of these two sets of conditions must be met. 2. start clock and maintain stable condition. 3. for the minimum of 200u s after stable power and clock(ck, ck ), then apply nop or deselect & take cke high. 4. wait minimum of 400ns then issue precharge al l command. nop or desel ect applied during 400ns period. 5. issue emrs(2) command. (to issue emrs(2) command, provide ?low? to ba0, ?high? to ba1.) 6. issue emrs(3) command. (to issue emrs(3) command, provide ?high? to ba0 and ba1.) 7. issue emrs to enable dll. (to issue "dll enable" command, provide "low" to a0, "high" to ba0 and "low" to ba1 and a12.) 8. issue a mode register set command for ?dll reset?. (to issue dll reset command, prov ide "high" to a8 and "low" to ba0-1) 9. issue precharge all command. 10. issue 2 or more auto-refresh commands. 11. issue a mode register set command with low to a8 to initialize device operation. (i.e. to program operating parameters without resetting the dll. 12. at least 200 clocks after step 8, execute ocd calibration ( off chip driver impedance adjustment ). if ocd calibration is not used, emrs ocd default command (a9=a8= a7=1) followed by emrs ocd
10 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb calibration mode exit command (a9=a8=a7=0) must be issued with other operating parameters of emrs. 13. the ddr2 sdram is now ready for normal operation. *1) to guarantee odt off, vref must be valid and a low level must be applied to the odt pin. programming the mode register for application flexibility, burst length, burst type, cas latency, dll reset function, write recovery time(twr) are user defined variables and must be programmed with a mode register set (mrs) command. addition- ally, dll disable function, driver im pedance, additive cas latency, odt( on die termination), single-ended strobe, and ocd(off chip driver impedance adjustment) are also user defined variables and must be pro- grammed with an extended mode register set (emrs) command. contents of the mode register(mr) or extended mode registers(emr(#)) can be altered by re-executing the mrs and emrs commands. if the user chooses to modify only a subset of the mrs or emrs variables, all variables must be redefined when the mrs or emrs commands are issued. mrs, emrs and reset dll do not affe ct array contents, which means rein itialization including those can be executed any time after power-up without affecting array contents. initialization sequence after power up /ck ck cke command pre all pre all emrs mrs ref ref mrs emrs emrs any cmd dll enable dll reset ocd default ocd cal. mode exit follow ocd flowchart 400ns trfc trfc trp trp tmrd tmrd tmrd toit min. 200 cycle nop odt tcl tch tis
11 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 ddr2 sdram mode register set (mrs) the mode register stores the data for controlling the various operating modes of ddr2 sdram. it controls cas latency, burst length, burst sequence, test mode, dll reset, twr and various vendor specific options to make ddr2 sdram useful for various applications. the default value of the mode register is not defined, therefore the mode register must be written after powe r-up for proper operation. the mode register is written by asserting low on cs , ras , cas , we , ba0 and ba1, while controlling the state of address pins a0 ~ a15. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the mode reg- ister. the mode register set command cycle time (tmrd) is required to complete the write operation to the mode register. the mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all ba nks are in the precharge state. the mode register is divided into various fields depending on functionality. burst length is defined by a0 ~ a2 with options of 4 and 8 bit burst lengths. the burst length decodes are co mpatible with ddr sdram. burst address sequence type is defined by a3, cas latency is defined by a4 ~ a6. the ddr2 doesnt support half clock latency mode. a7 is used for test mode. a8 is used for dll reset. a7 must be set to low for normal mrs operation. write recov- ery time twr is defined by a9 ~ a11. refer to the table for specific codes. address field cas laten cy a 6 a 5 a 4 latenc y 0 0 0 reserved 0 0 1 reserved 0 1 0 reserved 011 3 100 4 101 5 110 6 1 1 1 reserved a 7 mode 0 normal 1test a 3 burst t ype 0 sequential 1 interleave a 8 dll re set 0no 1yes mode register ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 tm cas latency bt dll 0* 1 wr write reco very for au top recharge a 11 a 10 a 9 wr(cycle s) 0 0 0 reserved 001 2 010 3 011 4 100 5 101 6 1 1 0 reserved 1 1 1 reserved a 15 * 1 ~a 13 0 burst length burs t le ng th a 2 a 1 a 0 bl 0104 0118 *1 : a13 is reserved for future use and must be programmed to 0 when setting the mode register. ba2 and a14 are not used for 512mb, but used for 1gb and 2gb ddr2 sdrams. a15 is reserved for future usage. *2 : wr(write recovery for autoprecharge) min is determine d by tck max and wr max is determined by tck min. wr in clock cycles is calculated by dividing twr (in ns) by tck (in ns) and rounding up a non-integer value to the next integer (wr[cycles] = twr(ns)/tck(ns)). the mode reg ister must be programmed to this value. this is also used with trp to determine tdal. ba1 ba0 mrs mode 00 mrs 01 emrs(1) 1 0 emrs(2): reserved 1 1 emrs(3): reserved *2 a 12 pd a 12 active p ower do wn exit time 0 fast exit(use t xard ) 1 slow exit(use t xards ) ba 2 * 1 0* 1
12 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb ddr2 sdram extended mode register set emrs(1) the extended mode register(1) stores the data for enabli ng or disabling the dll, output driver strength, odt value selection and additive latency. th e default value of the extended mode register is not defined, therefore the extended mode register must be written after po wer-up for proper operation. the extended mode register is written by asserting low on cs , ras , cas , we and high on ba0, while controlling the states of address pins a0 ~ a13. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register. the mode register set command cycle time (tmrd) must be satisfied to com- plete the write operation to the extended mode register. mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the pre- charge state. a0 is used for dll enable or disable. a1 is used for enabling a half strength data-output driver. a3~a5 determines the additive latency, a2 and a6 are used for odt value selection, a7~a9 are used for ocd control, a10 is used for dqs# disa ble and a11 is used for rdqs enable. dll enable/disable the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon returning to normal operation after having the dll disabled. the dll is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. any time the dll is enabled (and subsequently reset), 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synch ronized with the external clock. failing to wait for syn- chronization to occur may result in a vi olation of the tac or tdqsck parameters.
13 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 *1 : a13 is reserved for future use and must be programmed to 0 when se tting the mode register. ba2 and a14 are not used for 512mb, but used for 1gb and 2gb ddr2 sdrams. a15 is reserved for future use. *2 : optional for ddr2-400/533/667/800 address field rdqs extended mode register dll 0* 1 d.i.c ba 0 a 15 * 1 ~ a 13 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 0 dll en able 0enable 1 disable additive latency a 5 a 4 a 3 additive latency 000 0 001 1 010 2 011 3 100 4 101 5 1 1 0 reserved 1 1 1 reserved a: when adjust mode is issued, al from previously set value must be applied. b: after setting to default, ocd mode needs to be exited by setting a9-a7 to 000. refer to the following 3.2.2.3 section for detailed information a9 a8 a7 ocd calibr ation progra m 0 0 0 ocd calibration mode exit; maintain setting 0 0 1 drive(1) 0 1 0 drive(0) 100 adjust mode a 111 ocd calibration default b ocd program 1 dqs rtt rtt a1 outpu t dri ver impe denc e control drive r size 0 normal 100% 1 weak 60% a10 dqs 0 enable 1 disable * if rdqs is enabled, the dm function is disabled. rdqs is active for reads and dont care for writes. a11 rdqs enable 0 disable 1 enable ba 1 0 a6 a2 r tt ( nominal ) 00odt 01 1 0 150 ohm 1 1 50 ohm ( *2 ) ba1 ba0 mrs mode 00 mrs 01 emrs(1) 1 0 emrs(2) 1 1 emrs(3): reserved emrs(1) programming qoff a 12 a 12 qoff (optional) a a. outputs disabled - dqs, dqss, dqs s, rdqs, rdqs . this feature is used in conjunction with dimm idd meaurements when iddq is not desired to be included. 0 output buffer enabled 1 output buffer disabled a11 (rdqs enable) a10 (dqs enable) strob e fun cti on m atrix rdqs/dm rdqs dqs dqs 0 (disable) 0 (enable) dm hi-z dqs dqs 0 (disable) 1 (disable) dm hi-z dqs hi-z 1 (enable) 0 (enable) rdqs rdqs dqs dqs 1 (enable) 1 (disable) rdqs hi-z dqs hi-z ba 2 * 1 0 75 ohm disable
14 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb address field extended mode register(2) 0* 1 ba 0 a 15 * 2 ~ a 13 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 *1 ba0 and ba1 must be programmed to 0 when setting the mode register during initialization. *2 : ba2 and a14 are not used for 512mb, but used for 1gb and 2gb ddr2 sdrams. a15 is reserved for future usage. ba 1 1 emrs(2) programming: * 1 a 12 address field extended mode register(3) *1 : emrs(3) is reserved for future use and all bits except ba0 and ba1 must be programmed to 0 when setting the mode register during initialization. *2 : ba2 and a14 are not used for 512mb, but used for 1gb and 2gb ddr2 sdrams. a15 is reserved for future usage. emrs(3) programming: reserved * 1 0 * 2 ba 2 * 2 0 * 2 0* 1 ba 0 a 15 * 2 ~ a 13 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 ba 1 1 a 12 0 * 2 ba 2 * 2 0 * 2 pasr t he p a s r bits a llows the us e r to dyna mic a lly c us tomiz e the me mory a rra y s iz e to the a c tua l ne e ds . t his fe a ture allows the device to reduce s tandby current by refres hing only the memory arrays that contain es s ential data.t he refresh options are full array, one-half array, one-quarter array, three-fourth array, or none of the array. the mapping of these partitions can start at either the beginning or the end of the address map. please see the following table. pasr pasr[2] active section 000 full array 0 0 1 1/2 array (banks 0,1) 0 1 0 1/4 array (bank 0) 011 not defined 1 0 0 3/4 array (banks 1, 2, 3) 1 0 1 1/2 array (banks 2, 3) 1 1 0 1/4 array (bank 3) 111 not defined pasr[1] pasr[0]
15 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 off-chip driver (ocd) impedance adjustment ddr2 sdram supports driver calibration feature and the flow chart below is an example of the sequence. every calibration mode command should be followed by ?ocd calibration mode exit? before any other com- mand being issued. mrs should be set before entering ocd impedance adjustment and odt (on die termi- nation) should be carefully controlled depending on system environment. start emrs: drive(1) dq & dqs high:dqs low test emrs: ocd calibration mode exit emrs : enter adjust mode bl=4 code input to all dqs inc, dec, or nop emrs: ocd calibration mode exit emrs: drive(0) dq & dqs low:dqs high test emrs: ocd calibration mode exit emrs : enter adjust mode bl=4 code input to all dqs inc, dec, or nop emrs: ocd calibration mode exit need calibration need calibration emrs: ocd calibration mode exit all ok all ok emrs: ocd calibration mode exit end
16 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb extended mode register set for ocd impedance adjustment ocd impedance adjustment can be done using the following emrs mode. in drive mode all outputs are driven out by ddr2 sdram and drive of rdqs is dependent on emrs bit enabling rdqs operation. in drive(1) mode, all dq, dqs (and rdqs) signals are driven high and all dqs (and rdqs ) signals are driven low. in drive(0) mode, all dq, dqs (and rdqs) signals are driven low and all dqs (and rdqs) signals are driven high. in adjust mode, bl = 4 of operation code data must be used. in case of ocd calibration default, output driver characteristics have a nominal impedance value of 18 ohms during nominal temperature and voltage conditions. output driver characteristics for ocd calibration default are specified in the following table. ocd applies only to normal full strength output drive setting defined by emrs and if half strength is set, ocd default driver characteristics are not applicable. when ocd calibration adjust mode is used, ocd default output driver characteristics are not applicable. after ocd calibration is completed or driver strength is set to default, subsequent emrs commands not intended to adjust ocd characteristics must specify a7~a9 as ?000? in order to maintain the default or calibrated value. off- chip-driver program a9 a8 a7 operation 0 0 0 ocd calibration mode exit 0 0 1 drive(1) dq, dqs, (rdqs) high and dqs , (rdqs ) low 0 1 0 drive(0) dq, dqs, (rdqs) low and dqs , (rdqs ) high 1 0 0 adjust mode 1 1 1 ocd calibration default ocd impedance adjust to adjust output driver impedance, controllers must issue the adjust emrs command along with a 4 bit burst code to ddr2 sdram as in the following table. for this operation, burst length has to be set to bl = 4 via mrs command before activating ocd and controllers must drive the burst code to all dqs at the same time. dt0 is the table means all dq bits at bit time 0, dt1 at bit time 1, and so forth. the driver output imped- ance is adjusted for all ddr2 sdram dqs simultaneously and after ocd calibration, all dqs of a given ddr2 sdram will be adjusted to the same driver strength setting. the maximum step count for adjustment is 8 and when the limit is reached, further increment or decrement code has no effect. the default setting may be any step within the 8 step range.
17 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 off- chip-driver adjust program 4 bit burst code inputs to all dqs operation d t0 d t1 d t2 d t3 pull-up driver strength pull-down driver strength 00 0 0 nop (no operation) nop (no operation) 00 0 1 increase by 1 step nop 00 1 0 decrease by 1 step nop 01 0 0 nop increase by 1 step 10 0 0 nop decrease by 1 step 01 0 1 increase by 1 step increase by 1 step 01 1 0 decrease by 1 step increase by 1 step 10 0 1 increase by 1 step decrease by 1 step 10 1 0 decrease by 1 step decrease by 1 step other combinations reserved reserved for proper operation of adjust mode, wl = rl - 1 = al + cl -1 clocks and tds / tdh should be met as the fol- lowing timing diagram. input data pattern for adjustment, dt0 - dt3 is fixed and not affected by mrs addressing mode (i.e. sequential or interleave). burst length of 4 have to be programmed in the mrs for ocd impedance adjustment. nop em rs cm d ck dqs _i n dq_in tds tdh wl ocd adj ust mode ocd calibratio n mode exit twr emrs ck dqs nop nop nop nop nop d t0 d t1 d t2 d t3
18 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb drive mode drive mode, both drive(1) and drive(0), is used for controllers to measure ddr2 sdram driver impedance before ocd impedance adjustment. in this mode, all outputs are driven out toit after ?enter drive mode? command and all output drivers are turned-off toit after ?ocd calibration mode exit? command as the follow- ing timing diagram. emrs nop nop nop emrs cmd ck dqs dq enter drive mode ocd calibration mode exit toit hi-z dqs high for drive(1) dqs high & /dqs low for drive(1), dqs low & /dqs high for drive(0) hi -z dqs low for drive(0) toit ck dqs
19 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 on-die termination (odt) odt (on-die termination) is a new feature on ddr2 components that allows a dram to turn on/off termina- tion resistance for each dq, dqs, dqs and dm for x4 and dq, dqs, dqs , dm, rdqs (dm and rdqs share the same pin), and rdqs for x8 configuration via the odt control pin, where dqs is terminated only when enabled in the emrs by address bit a10 = 0. for x8 configuration rdqs is only terminated, when enabled in the emrs by address bits a10 = 0 and a11 = 1. for x16 configuration odt is applied to each udq, ldq, udqs, udqs , ldqs, ldqs , udm and ldm sig- nal via the odt control pin, where udqs and ldqs are terminated only when enabled in the emrs by address bit a10 = 0. the odt feature is designed to improve signal integrity of the memory channel by allowing the dram con- troller to independently turn on/off termination resistance for any or all dram devices. the odt function can be used for all active and standby modes. odt is turned off and not supported in self- refresh mode. funtional prepresentation of odt p dram input buffer input pin rval1 rval1 rval2 rval2 sw1 sw1 sw2 sw2 vddq vddq vssq vssq switch sw1 or sw2 is enabled by the odt pin. selection between sw1 or sw2 is determined by ?rtt (nominal)? in emrs address bits a6 & a2. target rtt = 0.5 * rval1 or 0.5 * rval2. the odt pin will be ignored if the extended mode register (emrs) is programmed to disable odt.
20 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb odt truth tables the odt truth table shows which of the input pins are terminated depending on the state of address bit a10 and a11 in the emrs for all three device organisations (x4, x8 and x16). to activate termination of any of these pins, the odt function has to be enabled in the emrs by address bits a6 and a2. input pin emrs adress bit a10 emrs adress bit a11 x4 components: dq0~dq3 x x dqs x x dqs 0 x dm x x x8 components: dq0~dq7 x x dqs x x dqs 0 x rdqs x 1 rdqs 0 1 dm x 0 x16 components: ldq0~ldq7 x x udq0~udq7 x x ldqs x x ldqs 0 x udqs x x udqs 0 x ldm x x udm x x
21 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 dc electrical characteristics and operation conditions: parameter / condition symbol min. nom. max. units notes rtt eff. impedance value for emrs(a6,a2)=0,1; 75 ohm rtt1(eff) 60 75 90 1 rtt eff. impedance value for emrs(a6,a2)=0,1; 150 ohm rtt2(eff) 120 150 180 1 deviation of vm with respect to vddq/2 delta vm - 6 + 6 %2 1) measurement definition for rtt(eff): apply vihac and vilac to test pin seperately, then measure current i(vihac) and i(vilac) respectively rtt(eff) = (vihac - vilac) /( i(vihac) - i(vilac)) 2) measurement defintion for vm: measure voltage (vm) at test pin (midpoint) with no load: delta vm =(( 2* vm / vddq) - 1 ) x 100% symbol parameter / condition min. max. units notes t aond odt turn-on delay 2 2 t ck t aon odt turn-on tac(min) tac(max ) + 1ns ns 1 t aonpd odt turn-on ( power -dow n mod es) tac(min) + 2ns 2 t ck + tac(max) + 1ns ns 3 t aofd odt turn-off delay 2.5 2.5 t ck t aof odt t urn-off tac (min) tac (max) + 0.6ns ns 2 t aofp d odt turn-off (pow er -down mo des ) tac(min) + 2ns 2.5 t ck + tac(max) + 1ns ns 3 t an pd odt to po wer down mode en try latency 3 t ck 4 t axp d odt p o we r do wn e x i t l a t e n c y 8 t ck 4 1) o d t tur n on ti me m in. is w hen th e de v ic e l eav e s hi gh i mped anc e and od t r es is tanc e begi ns to tur n on . odt tur n on time max . is when the odt resistance i s ful ly on. b oth a re m eas ur ed fr om t aond. 2) o dt tur n off ti me m in. is when th e de vice star s to tur n-off o dt resistanc e.. odt tur n off time max . is when the bus is in hi gh impedanc e. b oth ar e me as ur ed fr om t aofd. 3) for standar d active power-dow n - with mr s a12 = ?0? - the non pow er -dow n ti mi ngs (taond, taon, ta ofd and ta of) appl y 4) ta npd an d ta xpd define the t imi ng l imi t when ei ther power down mo de t iming s (taonpd, taofpd) or non-power down mode timi ng s ( tao nd, taofd) hav e to be appl ied ohm ohm ac electrical characteristics and operation conditions: rtt eff. impedance value for emrs(a6,a2)=1,1; 50 ohm 3) optional for ddr2-400/533/667/800 rtt3(eff) 40 50 60 1,3 ohm
22 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb odt timing for active / standby (idle) mode and standard active power-down mode odt timing for precharge power-down and low power power-down mode 1) b oth odt to p ower down entr y and e xit late ncy timing paramete r tanpd and tax p d are met, therefore non-p ower down mode timings have to be applied. 2) odt turn-on time (t aon,min ) is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max. (t aon,max ) is when the odt resistance is fully on. b oth are measured from t aond. 3) odt turn off time min. ( t aof,min ) is when the device starts to turn off the odt resistance. odt turn off time max. (t aof,max ) is when the bus is in high impedance. both a re measured from t aofd. cke dq odt1 odt ck, ck t0 rtt t is t is ta on(min) ta on(max) ta of(max) ta of(min) t is taond (2 tck) ta ofd (2. 5 tck) ta n pd ( >=3 tc k) taxp d (>=8 tck) t is t-3 t-1 t-2 t-6 t-4 t-5 t-n 1) both odt to power down entry and exit latencies tanpd and taxpd are not met, therefore power-down mode timings have to be applied. cke dq odt odt2 ck, ck t is t is ta ofp d , m in rtt ta onpd,min ta ofp d , m ax ta onp d,max ta n pd < 3 tc k taxp d < 8 tck t0 t1 t-1 t-2 t-3 t-5 t-4 t-6 t-7
23 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 bank activate command the bank activate command is issued by holding cas and we high with cs and ras low at the rising edge of the clock. the bank addresses ba0 and ba1 are used to select the desired bank. the row addresses a0 through a12 are used to determine which row to activate in the selected bank for x4 and x8 organised compo- nents. for x16 components row addresses a0 through a12 have to be applied. the bank activate command must be applied before any read or write operation can be executed. immediately after the bank active com- mand, the ddr2 sdram can accept a read or write command (with or without auto-precharge) on the fol- lowing clock cycle. if a r/w command is issued to a bank that has not satisfied the trcdmin specification, then additive latency must be programmed into the device to delay the r/w command which is internally issued to the device. the additive latency value must be chosen to assure trcdmin is satisfied. additive latencies of 0, 1, 2, 3 and 4 are supported. once a bank has been activated it must be precharged before another bank activate command can be applied to the same bank. the bank active and precharge times are defined as tras and trp, respectively. the minimum time interval between successive bank activate com- mands to the same bank is determined (trc). the minimum time interval between bank active commands, to any other bank, is the bank a to bank b delay time (trrd). bank activate command cycle: trcd = 3, al = 2, trp = 3, trrd = 2 address command t0 t2 t1 t3 t4 col. addr. bank a row addr. bank b col. addr. bank b internal ras-cas delay trcdmin. bank a to bank b delay trrd. activate bank b read a posted cas activate bank a read b posted cas read a begins row addr. bank a addr. bank a precharge bank a addr. bank b precharge bank b row addr. bank a activate bank a trp row precharge time (bank a) trc row cycle time (bank a) tn tn+1 tn+2 tn+3 act ras-ras delay trrd. tras row active time (bank a) additive latency al=2 ck, ck
24 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb read and write commands and access modes after a bank has been activated, a read or write cycle can be executed. this is accomplished by setting ras high, cs and cas low at the clock?s rising edge. we must also be defined at this time to determine whether the access cycle is a read operation (we high) or a write operation (we low). the ddr2 sdram provides a wide variety of fast access modes. a single read or write command will initiate a serial read or write opera- tion on successive clock cycles at data rates of up to 667mb/sec/pin for main memory. the boundary of the burst cycle is restricted to specific segments of the page length. for example, the 32mbit x 4 i/o x 4 bank chip has a page length of 1 kbyte (defined by ca0-ca9 & ca11). in case of a 4-bit burst operation (burst length = 4) the page length of 1 kbyte is divided into 512 uniquely addressable segments (4-bits x 4 i/o each). the 4-bit burst operation will occur entirely within one of the 512 segments (defined by ca0-ca8) beginning with the column address supplied to the device during the read or write command (ca0-ca9 & a11). the second, third and fourth access will also occur within this segment, however, the burst order is a function of the starting address, and the burst sequence. in case of a 8-bit burst operation (burst length = 8) the page length of 1 kbyte is divided into 256 uniquely addressable double segments (8-bits x 4 i/o each). the 8-bit burst operation will occur entirely within one of the 256 double segments (defined by ca0-ca7) beginning with the column address supplied to the deivce during the read or write command ( ca0-ca9 & ca11). a new burst access must not interrupt the previous 4 bit burst operation in case of bl = 4 setting. therefore the minimum cas to cas delay (tccd) is a minimum of 2 clocks for read or write cycles . for 8 bit burst operation (bl = 8 ) the minimum cas to cas delay (tccd) is 4 clocks for read or write cycles. burst interruption is allowed with 8 bit burst operation. for details see the ?burst interrupt? - section of this datasheet. read burst timing example : (cl = 3, al = 0, rl = 3, bl = 4) nop nop nop nop nop read a t0 t2 t1 t3 t4 t5 t6 t7 t12 cmd dq rb dqs, dqs read b nop dout a0 dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 dout b3 dout c0 dout c1 dout c2 dout c3 nop read c tccd tccd ck, ck
25 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 posted cas posted cas operation is supported to make command and data bus efficient for sustainable bandwidths in ddr2 sdram. in this operation, the ddr2 sdram allows a read or write command to be issued imme di- ately after the ras bank activate command (or any time during the ras to cas delay time, trcd, perio d). the command is held for the time of the additive latency (al) before it is issued inside the device. the re ad latency (rl) is the sum of al and the cas latency (cl). therefore if a user chooses to issue a read/wr ite command before the trcdmin, then al greater than 0 must be written into the emrs. the write laten cy (wl) is always defined as rl - 1 (read latency -1) where read latency is defined as the sum of addit ive latency plus cas latency (rl=al+cl). if a user chooses to issue a read command after the trcdm in period, the read latency is also defined as rl = al + cl. read followed by a write to the same bank, activate to read delay < trcdmin: al = 2 and cl = 3, rl = (al + cl) = 5, wl = (rl -1) = 4, bl = 4 dout0 dout1 dout2 dout3 cmd dq 0 2 34 5 6 7 89101112 -1 1 trcd al = 2 " trac" rl = al + cl = 5 cl = 3 wl = rl -1 = 4 din0 din1 din2 din3 postcas1 dqs, dqs activate read write bank a bank a bank a ck, ck read followed by a write to the same bank, activate to read delay < trcdmin: al = 2 and cl = 3, rl = (al + cl) = 5, wl = (rl -1) = 4, bl = 8 cmd dq 0 2 34 5 6 7 89101112 1 trcd al = 2 " trac" rl = al + cl = 5 cl = 3 wl = rl -1 = 4 postcas3 dqs, dqs activate read bank a bank a din0 din1 din2 din3 write bank a dout0 dout1 dout2 dout3 dout0 dout1 dout2 dout3 ck, ck
26 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb read followed by a write to the same bank, activate to read delay = trcdmin: al = 0, cl = 3, rl = (al + cl) = 3, wl = (rl -1) = 2, bl = 4 read followed by a write to the same bank, activate to read delay > trcdmin: al = 1, cl = 3, rl = 4, wl = 3, bl = 4 activate bank a 0 2 34 56 7 89101112 -1 1 cmd dq trcd>trcdmin. "trac" rl = 4 wl = 3 postcas5 dqs, dqs read bank a din0 din1 din2 din3 dout0 dout1 dout2 dou t3 write bank a ck, ck activate bank a 0 2 34 56 7 89101112 -1 1 cmd dq trcd>trcdmin. "trac" rl = 4 wl = 3 postcas5 dqs, dqs read bank a din0 din1 din2 din3 dout0 dout1 dout2 dou t3 write bank a ck, ck
27 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 burst mode operation burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). the parameters that define how the burst mode will operate are burst sequence and burst length. the ddr2 sdram supports 4 bit and 8 bit burst modes only. for 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. the burst length is programmable and defined by the addresses a0 ~ a2 of the mrs. the burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (a3) of the mrs. seamless burst read or write operations are supported. interruption of a burst read or write oper- ation is prohibited, when burst length = 4 is programmed. for burst interruption of a read or write burst when burst length = 8 is used, see the ?burst interruption ? section of this datasheet. a burst stop command is not supported on ddr2 sdram devices. burst length and sequence gq burst length starting address (a2 a1 a0) sequential addressing (decimal) interleave addressing (decimal) 4 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 note: 1) page length is a function of i/o organization 128mb x 4 organization (ca0-ca9, ca11); page length = 1 kbyte 64mb x 8 organization (ca0-ca9 ); page length = 1 kbyte 32mb x 16 organization (ca0-ca9); page length = 2 kbyte 2) order of burst access for sequential addressing is ?nibble-based? and therefore different from sdr or ddr components
28 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb burst read command the burst read command is initiated by having cs and cas low while holding ras and we high at the rising edge of the clock. the address inputs determine the starting column address for the burst. the delay from the start of the command until the data from the first cell appears on the outputs is equal to the value of the read latency (rl). the data strobe output (dqs) is driven low one clock cycle before valid data (dq) is driven onto the data bus. the first bit of the burst is synchronized with the rising edge of the data strobe (dqs). each sub- sequent data-out appears on the dq pin in phase with the dqs signal in a source synchronous manner. the rl is equal to an additive latency (al) plus cas latency (cl). the cl is defined by the mode register set (mrs). the al is defined by the extended mode register set (emrs). basic burst read timing ck, ck dqs, dqs dq ck ck dqs dqs t ch t cl t rpre t dqsqmax t qh t rpst dqsqmax t qh t do do do do do don?t care burst read operation: rl = 5 (al = 2, cl = 3, bl = 4) nop nop nop nop nop nop nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 5 al = 2 cl = 3 nop <= tdqsck cmd dq bread523 dqs, dqs post cas ck, ck
29 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 burst read operation: rl = 3 (al = 0, cl = 3, bl = 8) cmd nop nop nop nop nop nop dq?s nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 3 cl = 3 nop <= tdqsck bread303 dqs, dqs dout a4 dout a5 dout a6 dout a7 ck, ck burst read followed by burst write : rl = 5, wl = (rl-1) = 4, bl = 4 nop posted cas write a nop nop nop nop nop read a posted cas t0 t1 dout a0 dout a1 dout a2 dout a3 rl = 5 nop cmd dq brbw514 t3 t4 t5 t6 t7 t8 t9 din a0 din a1 din a2 din a3 dqs, dqs wl = rl - 1 = 4 bl/2 + 2 ck, ck the minimum time from the burst read command to the burst write command is defined by a read-to-write turn-around time, which is bl/2 + 2 clocks.
30 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb seamless burst read operation : rl = 5, al = 2, cl = 3, bl = 4 nop nop nop nop nop nop nop read a post cas read b post cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 dout b3 rl = 5 al = 2 cl = 3 sbr523 cmd dq dqs, dqs ck, ck the seamless burst read operation is supported by enabling a read command at every bl / 2 number of clocks. this operation is allowed regardless of same or different banks as long as the banks are activated. seamless burst read operation : rl = 3, al = 0, cl = 3, bl = 8 (non interrupting) nop nop nop read a post cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 dout a4 dout a5 dout a4 dout a7 rl = 3 cl = 3 sbr_bl8 cmd dq dqs, dqs read b post cas dout b0 dout b1 dout b2 dout b3 dou nop nop nop nop no t9 ck, ck the seamless, non interrupting 8-bit burst read operation is supported by enabling a read command at every bl / 2 number of clocks. this operation is allowed regardless of same or different banks as long as the banks are activated.
31 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 burst write command the burst write command is initiated by having cs , cas and we low while holding ras high at the rising edge of the clock. the address inputs determine the starting column address. write latency (wl) is defined by a read latency (rl) minus one and is equal to (al + cl -1). a data strobe signal (dqs) should be driven low (preamble) one clock prior to the wl. the first data bit of the burst cycle must be applied to the dq pins at the first rising edge of the dqs following the preamble. the tdqss specification must be satisfied for write cycles. the subsequent burst bit data are issued on successive edges of the dqs until the burst length is completed. when the burst has finished, any additional data supplied to the dq pins will be ignored. the dq signal is ignored after the burst write operation is complete. the time from the completion of the burst write to bank precharge is named ?write recovery time? (twr) and is the time needed to store the write data into the memory array. twr is an analog timing parameter (see the ac table in this specification) and is not the pro - grammed value for wr in the mrs. basic burst write timing dqs, dqs dqs dqs t dqsh t dqsl t wpre wpst t din din din din t ds t dh burst write operation : rl = 5 (al = 2, cl = 3), wl = 4, bl = 4 nop nop nop nop nop precharge nop write a post cas t0 t2 t1 t3 t4 t5 t6 t7 t9 wl = rl-1 = 4 bw543 cmd dq nop din a0 din a1 din a2 din a3 <= tdqss twr completion of the burst write dqs, dqs ck, ck
32 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb burst write operation : rl = 3 (al = 0, cl = 3), wl = 2, bl = 4 nop nop nop nop nop write a post cas t0 t2 t1 t3 t4 t5 t6 t7 t9 wl = rl-1 = 2 bw322 cmd dq nop din a0 din a1 din a2 din a3 twr completion of the burst write <= tdqss precharge bank a activate trp dqs, dqs ck, ck burst write followed by burst read : rl = 5 (al = 2, cl = 3), wl = 4, twtr = 2, bl = 4 nop nop nop nop nop read a post cas bwbr cmd dq nop din a0 din a1 din a2 din a3 al=2 cl=3 nop nop twtr t0 t2 t1 t3 t4 t5 t6 t7 t8 t9 write to read = (cl - 1)+ bl/2 +twtr(2) = 6 dqs, dqs wl = rl - 1 = 4 rl=5 ck, ck the minimum number of clocks from the burst write command to the burst read command is (cl - 1) +bl/2 + twtr where twtr is the write-to-read turn-around time twtr expressed in clock cycles. the twtr is not a write recovery time (twr) but the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array.
33 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 nop nop nop nop nop nop nop din a0 din a1 din a2 din a3 write a post cas wl = rl - 1 = 4 write b post cas din b0 din b1 din b2 din b3 t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq sbr dqs, dqs ck, ck seamless burst write operation: rl=5, wl=4, bl=4 the seamless burst write operation is supported by enabling a write command every bl / 2 number of clocks . this operation is allowed regardless of same or different banks as long as the banks are activated. nop nop nop nop nop nop nop write a wl = rl - 1 = 2 t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq sbw_bl8 dqs, dqs write b din a0 din a1 din a2 din a3 din a4 din a5 din a5 din a7 din b0 din b1 din b2 din b3 din b4 din b5 din ck, ck seamless burst write operation: rl=3, wl=2, bl=8, noninterrupting the seamless, non interrupting 8-bit burst write operation is supported by enabling a write command at every bl / 2 number of clocks. this operation is allowed regardless of same or different banks as long as the banks are activated.
34 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb write data mask one write data mask input (dm) for x4 and x8 components and two write data mask inputs (ldm, udm) for x16 components are supported on ddr2 sdrams, consistent with the implementation on ddr sdrams. it has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. data mask is not used during read cycles. if dm is high during a write burst coincident with the write data, the write data bit is not written to the memory. for x8 components the dm function is disabled, when rdqs / rdqs are enabled by emrs. . write data mask timing dqs, dqs dqs dqs t dqsh t dqsl t wpre wpst t dq din din t ds dh dm don?t care din din t . burst write operation with data mask : rl = 3 (al = 0, cl = 3), wl = 2, twr = 3 , bl = 4 nop nop nop nop nop write a t0 t2 t1 t3 t4 t5 t6 t7 t9 wl = rl-1 = 2 dm cmd dq nop twr <= tdqss precharge bank a activate trp dqs, dqs dm din a0 din a3 ck, ck din a1 din a2
35 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 burst interruption interruption of a read or write burst is prohibited for burst length of 4 and only allowed for burst length of 8 under the following conditions: 1. a read burst of 8 can only be interrupted by another read command. read burst interruption by a write or precharge command is prohibited. 2. a write burst of 8 can only be interrupted by another write command. write burst interruption by a read or precharge command is prohibited. 3. read burst interrupt must occur exactly two clocks after the previous read command. any other read burst interrupt timings are prohibited. 4. write burst interrupt must occur exactly two clocks after the previous write command. any other read burst interrupt timings are prohibited. 5. read or write burst interruption is allowed to any bank inside the ddr2 sdram. 6. read or write burst with auto-precharge enabled is not allowed to be interrupted. 7. read burst interruption is allowed by a read with auto-precharge command. 8. write burst interruption is allowed by a write with auto-precharge command. 9. all command timings are referenced to burst length set in the mode register. they are not referenced to the actual burst. for example, minimum read to precharge timing is al + bl/2 where bl is the burst length set in the mode reg- ister and not the actual burst (which is shorter because of interrupt). minimum write to precharge timing is wl + bl/ 2 + twr, where twr starts with the rising clock after the un-interrupted burst end and not form the end of the actual burst end. read burst interrupt timing example : (cl = 3, al = 0, rl = 3, bl = 8) nop nop nop nop nop nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq rbi dqs, dqs read b nop dout a0 dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 dout b3 dout b4 dout b5 dout b6 dout b ck, ck
36 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb write burst interrupt timing example : ( cl = 3, al = 0, wl = 2, bl = 8) nop nop nop nop nop write a t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq wbi dqs, dqs nop din a0 din a1 din a2 din a3 din b0 din b1 din b2 din b3 dout b4 din b5 din b6 din b7 write b ck, ck nop
37 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge com- mand is triggered when cs , ras and we are low and cas is high at the rising edge of the clock. the pre- charge command can be used to precharge each bank independently or all banks simultaneously. three address bits a10, ba1 and ba0 are used to define which bank to precharge when the command is issued. bank selection for precharge by address bits a10 b a 1 b a 0 p r e c h a r g e bank(s) low low low ba nk 0 only low low high bank 1 only low high low ba nk 2 only low high high bank 3 only hig h don?t c are don?t c are all banks burst read operation followed by a precharge the following rules apply as long as the trtp timing parameter - internal read to precharge command delay time - is less or equal two clocks, which is the case for operating frequencies less or equal 266 mhz (ddr2 400 and 533 speed sorts): minimum read to precharge command spacing to the same bank = al + bl/2 clocks. for the earliest possi- ble precharge, the precharge command may be issued on the rising edge which is ?additive latency (al) + bl/2 clocks? after a read command, as long as the minimum tras timing is satisfied. a new bank active command may be issued to the same bank if the following two conditions are satisfied simultaneously: (1) the ras precharge time (trp) has been satisfied from the clock at which the precharge begins. (2) the ras cycle time (trcmin) from the previous bank activation has been satisfied. for operating frequencies higher than 266 mhz, trtp becomes > 2 clocks and one additional clock cycle has to be added for the minimum read to precharge command spacing, which now becomes al + bl/2 + 1 clocks.
38 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb burst read operation followed by precharge: rl = 4 (al = 1, cl = 3), bl = 4, trtp <= 2 clocks burst read operation followed by precharge: rl = 4 (al = 1, cl = 3), bl = 8, trtp <= 2 clocks nop precharge nop bank a activate nop nop read a post cas t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq nop al + bl/2 clks dout a0 dout a1 dout a2 dout a3 al = 1 cl = 3 rl = 4 >=tras cl = 3 trp dqs, dqs nop >=trc >=trtp ck, ck nop nop nop read a post cas t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p413(8) nop al + bl/2 clks dout a0 dout a1 dout a2 dout a3 al = 1 cl = 3 rl = 4 >=tras cl = 3 trp dqs, dqs nop >=trc >=trtp dout a4 dout a5 dout a6 dout a7 precharge nop bank a activate first 4-bit prefetch second 4-bit prefetch ck, ck
39 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 nop nop nop bank a activate nop nop read a post cas t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p523 nop al + bl/2 clks dout a0 dout a1 dout a2 dout a3 al = 2 cl = 3 rl = 5 >=tras cl = 3 trp precharge dqs, dqs >=trc >=trtp ck, ck nop nop nop read a post cas t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p624 nop al + bl/2 clocks dout a0 dout a1 dout a2 dout a3 al = 2 cl = 4 rl = 6 >=tras cl = 4 trp precharge a bank a activate dqs, dqs nop nop >=trc >=trtp ck, ck burst read operation followed by precharge: rl=5(al=2, cl=3), bl=4, trtp<=2 clocks burst read operation followed by precharge: rl=6(al=2, cl=4), bl=4, trtp<=2 clocks
40 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb nop nop nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p404(8) nop al + bl/2 clks + 1 dout a0 dout a1 dout a2 dout a3 cl = 4 rl = 4 >=tras trp dqs, dqs nop >=trtp dout a4 dout a5 dout a6 dout a7 precharge nop bank a activate first 4-bit prefetch second 4-bit prefetch ck, ck burst read operation followed by precharge: rl=4, (al=0, cl=4), bl=8, trtp>2 clocks
41 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 burst write followed by precharge minimum write to precharge command spacing to the same bank = wl + bl/2 + twr . for write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge command can be issued. this delay is known as a write recovery time (t wr ) referenced from the completion of the burst write to the precharge command. no precharge command should be issued prior to the twr delay, as ddr2 sdram does not support any burst interrupt by a precharge command. twr is an analog timing parameter (see the ac table in this datasheet) and is not the programmed value for twr in the mrs. burst write followed by precharge : wl = (rl - 1) = 3, bl = 4, twr = 3 burst write followed by precharge : wl = (rl - 1) = 4, bl = 4, twr = 3 nop nop nop nop nop write a post cas t0 t2 t1 t3 t4 t5 t6 t7 t8 wl = 3 bw-p3 cmd dq nop din a0 din a1 din a2 din a3 twr completion of the burst write precharge a nop dqs, dqs ck, ck nop nop nop nop nop write a post cas t0 t2 t1 t3 t4 t5 t6 t7 t9 wl = 4 bw-p4 cmd dq nop din a0 din a1 din a2 din a3 twr completion of the burst write precharge a nop dqs, dqs ck, ck
42 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb auto-precharge operation before a new row in an active bank can be opened, the active bank must be precharged using either the pre- charge command or the auto-precharge function. when a read or a write command is given to the ddr2 sdram, the cas timing accepts one extra address, column address a10, to allow the active bank to auto- matically begin precharge at the earliest possible moment during the burst read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. if a10 is high when the read or write com- mand is issued, then the auto-precharge function is enabled. during auto-precharge, a read command will execute as normal with the exception that the active bank will begin to precharge internally on the rising edge which is cas latency (cl) clock cycles before the end of the read burst. auto-precharge is also implemented for write commands.the precharge operation engaged by the auto-precharge command will not begin until the last datga of the write burst sequence is properly stored in the memory array. this feature allows the pre- charge operation to be partially or completely hidden during burst read cycles (dependent upon cas latency) thus improving system performance for random data access. the ras lockout circuit internally delays the precharge operation until the array restore operation has been completed so that the auto-precharge com- mand may be issied with any read or write command. burst read with auto-precharge if a10 is high when a read command is issued, the read with auto-precharge function is engaged. the ddr2 sdram starts an auto-precharge operation on the rising edge which is (al + bl/2) cycles later from the read with ap command if tras(min) and trtp are satisfied. if tras(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until tras(min) is satisfied. if trtp(min) is not satis- fied at the edge, the start point of auto-precharge operation will be delayed until trtp(min) is satisfied. in case the internal precharge is pushed out by trtp, trp starts at the point where the internal precharge happens (not at the next rising clock edge after this event). so for bl = 4 the minimum time from read with auto-precharge to the next activate command becomes al + trtp + trp. for bl = 8 the time from read with auto-precharge to the next activate command is al + 2 + trtp + trp. note that both parameters trtp and trp have to be rounded up to the next integer value. in any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch. a new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously: (1) the ras precharge time (trp) has been satisfied from the clock at which the auto-precharge begins. (2) the ras cycle time (trc) from the previous bank activation has been satisfied.
43 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 burst read with auto-precharge followed by an activation to the same bank (trc limit) rl = 5 (al = 2, cl = 3), bl = 4, trtp <= 2 clocks burst read with auto-precharge followed by an activation to the same bank (tras limit): rl = 5 ( al = 2, cl = 3), bl = 4, trtp <= 2 clocks nop nop nop nop bank activate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 5 al = 2 cl = 3 nop cmd dq br-ap5231 a10 ="high" trp auto-precharge begins dqs, dqs tras trcmin. nop al + bl/2 ck, ck nop nop nop nop bank activate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 5 al = 2 cl = 3 nop cmd dq br-ap5232 a10 ="high" trp auto-precharge begins dqs, dqs trc tras(min) nop ck, ck
44 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb nop nop nop nop bank activate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 4 al = 1 cl = 3 nop cmd dq br-ap413(8)2 a10 ="high" trp auto-precharge begins dqs, dqs nop dout a4 dout a5 dout a6 dout a7 first 4-bit prefetch second 4-bit prefetch >= trtp al + bl/2 ck, ck nop nop nop nop bank activate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 4 al = 1 cl = 3 nop cmd dq br-ap4133 a10 ="high" auto-precharge begins dqs, dqs nop first 4-bit prefetch trtp al + trtp + trp trp ck, ck burst read with auto-precharge followed by an activation to the same bank: rl=4(al=1, cl=3), bl=8, trtp<=2 clocks burst read with auto-precharge followed by an activation to the same bank: rl=4(al=1, cl=3), bl=8, trtp>2 clocks
45 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 burst write with auto-precharge if a10 is high when a write command is issued, the write with auto-precharge function is engaged. the ddr2 sdram automatically begins precharge operation after the completion of the write burst plus the write recovery time delay (wr), programmed in the mrs register, as long as tras is satisfied. the bank undergoing auto-precharge from the completion of the write burst may be reactivated if the following two con- ditions are satisfied. (1) the last data-in to bank activate delay time (tdal = wr + trp) has been satisfied. (2) the ras cycle time (trc) from the previous bank activation has been satisfied. in ddr2 sdrams the write recovery time delay (wr ) has to be programmed into the mrs mode register. as long as the analog twr timing parameter is not violated, wr can be programmed between 2 and 6 clock cycles. minimum write to activate command spacing to the same bank = wl + bl/2 + tdal. examples: burst write with auto-precharge (trc limit) : wl = 2, tdal = 6 (wr = 3, trp = 3) , bl = 4 nop nop nop nop nop bank a activate nop write a t0 t2 t1 t3 t4 t5 t6 t7 nop cmd dq bw-ap223 a10 ="high" trp auto-precharge begins din a0 din a1 din a2 din a3 wl = rl-1 = 2 wr trcmin. dqs, dqs completion of the burst write tdal >=trasmin. ck, ck
46 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb nop nop nop nop nop bank a activate nop write a posted cas t0 t3 t4 t5 t6 t7 t12 nop cmd dq bw-ap423 a10 ="high" trp auto-precharge begins din a0 din a1 din a2 din a3 wl = rl-1 = 4 wr >=trc t9 t8 completion of the burst write dqs, dqs tdal >=tras ck, ck burst write with auto-precharge (wr+trp limit): wl=4, tdal=6(wr=3, trp=3), bl=4
47 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 concurrent auto-precharge ddr2 devices support the ?concurrent auto-precharge? feature. a read with auto-precharge enabled, or a write with auto-precharge enabled, may be followed by any command to the other bank, as long as that com- mand does not interrupt the read or write data transfer, and all other related limitations (e.g. contention between read data and write data must be avoided externally and on the internal data bus. the minimum delay from a read or write command with auto-precharge enabled, to a command to a different bank, is summarized in the table below. as defined, the wl = rl - 1 for ddr2 devices which allows the com- mand gap and corresponding data gaps to be minimized. from command to command (different bank, non-interrupting command) minimum delay with concurrent auto-pre- charge support units write w/ap read or read w/ap (cl -1) + (bl/2) + twtr tck write ot write w/ap bl/2 tck precharge or activate 1 tck read w/ap read or read w/ap bl/2 tck write or write w/ap bl/2 + 2 tck precharge or activate 1 tck
48 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb refresh sdrams require a refresh of all rows in any rolling 64 ms interval. each refresh is generated in one of two ways : by an explicit auto-refresh command, or by an internally timed event in self-refresh mode. dividing the number of device rows into the rolling 64 ms interval defined the average refresh interval trefi, which is a guideline to controlles for distributed refresh timing. for example, a 512mbit ddr2 sdram has 8192 rows resulting in a trefi of 7,8 s. auto-refresh command auto-refresh is used during normal operation of the ddr2 sdrams. this command is nonpersistent, so it must be issued each time a refresh is required. the refresh addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto-refresh command. the ddr2 sdram requires auto-refresh cycles at an average periodic interval of trefi (maximum). when cs , ras and cas are held low and we high at the rising edge of the clock, the chip enters the auto- refresh mode. all banks of the sdram must be precharged and idle for a minimum of the precharge time (t rp ) before the auto-refresh command can be applied. an internal address counter supplies the addresses during the refresh cycle. no control of the external address bus is required once this cycle has started. when the refresh cycle has completed, all banks of the sdram will be in the precharged (idle) state. a delay between the auto-refresh command and the next activate command or subsequent auto-refresh com- mand must be greater than or equal to the auto-refresh cycle time (t rfc ). to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram, meaning that the maximum absolute interval between any auto-refresh command and the next auto-refresh command is 9 * trefi. t0 t2 t1 t3 ar ck, ck cmd precharge > = t rp nop auto refresh any nop > = t rfc > = t rfc auto refresh nop nop nop cke "high"
49 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 self-refresh command the self-refresh command can be used to retain data, even if the rest of the system is powered down. when in the self-refresh mode, the ddr2 sdram retains data without external clocking. the ddr2 sdram device has a built-in timer to accommodate self-refresh operation. the self-refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. odt must be turned off before issuing self refresh command, by either driving odt pin low or using emrs command. once the command is registered, cke must be held low to keep the device in self-refresh mode. when the ddr2 sdram has entered self-refresh mode all of the external control signals, except cke, are disabled. the clock is internally disabled during self-refresh operation to save power. the user may change the external clock frequency or halt the external clock one clock after self-refresh entry is registered, how- ever, the clock must be restarted and stable before the device can exit self-refresh operation. once self- refresh exit command is registered, a delay equal or longer than the txsnr or txsrd must be satisfied before a valid command can be issued to the device. cke must remain high for the entire self-refresh exit period (txsnr or txsrd) for proper operation. nop or deselect commands must be registered on each positive clock edge during the self-refresh exit interval. since the odt function is not supported during self- refresh operation, odt has to be turned off taofd before entering self-refresh mode and can be turned on again when the txsrd timing is satisfied. * = device must be in the ?all banks idle? state to entering self refresh mode. odt must be turned off prior to entering self refresh mode. txsrd has to be satisfied for a read or a read with auto-precharge command. txsnr has to be satisfied for any command except a read or a read with auto-precharge command. ck/ck t1 t3 t2 ck/ck may be halted ck/ck must be stable cke >=txsrd >= txsnr tn tr tm t5 t4 trp* tis taofd cmd self refresh entry nop non-read command read command t0 tis tis odt
50 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb power-down power-down is synchronously entered when cke is registered low along with nop or deselect command. no read or write operation may be in progress when cke goes low. these operations are any of the follow- ing: read burst or write burst and recovery. cke is allowed to go low while any of other operations such as row activation, precharge or autoprecharge, mode register or extended mode register command time, or autorefresh is in progress. the dll should be in a locked state when power-down is entered. otherwise dll should be reset after exiting power-down mode for proper read operation. if power-down occurs when all banks are precharged, this mode is referred to as precharge power-down ; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down . for active power-down two different power saving modes can be selected within the mrs register, address bit a12. when a12 is set to ?low? this mode is referred as ?standard active power-down mode? and a fast power-down exit timing defined by the txard timing parameter can be used. when a12 is set to ?high? this mode is referred as a power saving ?low power active power-down mode?. this mode takes longer to exit from the power-down mode and the txards timing parameter has to be satisfied. entering power-down deactivates the input and output buffers, excluding ck, ck , odt and cke. also the dll is disabled upon entering precharge power-down or slow exit active power-down, but the dll is kept enabled during fast exit active power-down. in power-down mode, cke low and a stable clock signal must be maintained at the inputs of the ddr2 sdram, and all other input signals are ?don?t care?. power-down dura- tion is limited by 9 times trefi of the device. the power-down state is synchronously exited when cke is registered high (along with a nop or deselect command). a valid, executable command can be applied with power-down exit latency, txp, txard or txards, after cke goes high. power-down exit latencies are defined in the ac spec table of this data sheet. power-down entry active power-down mode can be entered after an activate command. precharge power-down mode can be entered after a precharge, precharge-all or internal precharge command. it is also allowed to enter power- mode after an auto-refresh command or mrs / emrs command when tmrd is satisfied. active power-down mode entry is prohibited as long as a read burst is in progress, meaning cke should be kept high until the burst operation is finished. therefore active power-down mode entry after a read or read with auto-precharge command is allowed after rl + bl/2 is satisfied. active power-down mode entry is prohibited as long as a write burst and the internal write recovery is in progress. in case of a write command, active power-down mode entry is allowed when wl + bl/2 + twtr is satisfied. in case of a write command with auto-precharge, power-down mode entry is allowed after the internal pre- charge command has been executed, which is wl + bl/2 + wr starting from the write with auto-precharge command. in case the ddr2 sdram enters the precharge power-down mode .
51 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 active power-down mode entry and exit after an activate command active power-down mode entry and exit after a read burst: rl = 4 (al = 1, cl =3), bl = 4 note: active power-down mode exit timing txard (?fast exit?) or txards (?slow exit?) depends on the programmed state in the mrs, address bit a12. nop nop activate t0 t2 t1 cmd nop tn tn+1 cke active power-down entry nop nop act.pd 0 tis tn+2 tis active power-down exit valid command txard or txards *) ck, ck note: active power-down mode exit timing txard (?fast exit?) or txards (?slow exit?) depends on the programmed state in the mrs, address bit a12. nop nop read t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 4 cl = 3 cmd dq dqs, dqs nop nop nop nop nop nop tn tn+1 cke al = 1 active power-down entry rl + bl/2 nop nop act.pd 1 tis tn+2 tis active power-down exit valid command txard or txards *) ck, ck read w/ap
52 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb active power-down mode entry and exit after a write burst: wl = 2, twtr = 2, bl = 4 precharge power down mode entry and exit note: active power-down mode exit timing txard (?fast exit?) or txards (?slow exit?) depends on the programmed state in the mrs, address bit a12. nop nop write t0 t2 t1 t3 t4 t5 t6 t7 dout a0 dout a1 dout a2 dout a3 cmd dq dqs, dqs nop nop nop nop nop nop tn tn+1 cke wl = rl - 1 = 2 active power-down entry wl + bl/2 + twtr nop nop act.p twtr tis tn+2 tis valid comman active power-down exit txard or txards *) ck, ck txp nop nop precharge *) t0 t2 t1 cmd nop nop tn tn+1 cke precharge power-down entry nop nop prepd tis tn+2 tis precharge power-down exit valid command trp nop t3 *) "precharge" may be an external command or an internal precharge following write with ap. ck, ck
53 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 no operation command the no operation command should be used in cases when the sdram is in a idle or a wait state. the pur- pose of the no operation command is to prevent the sdram from registering any unwanted commands between operations. a no operation command is registered when cs is low with ras , cas , and we held high at the rising edge of the clock. a no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. deselect command the deselect command performs the same function as a no operation command. deselect command occurs when cs is brought high, the ras , cas , and we signals become don?t care. input clock frequency change during operation the dram input clock frequency can be changed under the following conditions: a) during self-refresh operation b) dram is in precharged power-down mode and odt is completely turned off. the ddr2-sdram has to be in precharged power-down mode and idle. odt must be allready turned off and cke must be at a logic ?low? state. after a minimum of two clock cycles after trp and taofd have been sat- isfied the input clock frequency can be changed. a stable new clock frequency has to be provided, before cke can be changed to a ?high? logic level again. after txp has been satisfied a dll reset command via emrs has to be issued. during the following dll re-lock period of 200 clock cycles, odt must remain off. after the dll-re-lock period the dram is ready to operate with the new clock frequency. ck cke t0 t4 tx+1 ty ty+1 ty+2 t1 t2 tx ck valid dll nop 200 clocks frequency change ty+3 tz nop nop nop nop reset t r p clock frequency change in precharge power down mode txp occurs here t a o f d stable new clock before power down exit odt is off during dll reset minmum 2 clocks required before changing frequency odt ras, cs cas, we ty+4
54 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb asynchronous cke low event dram requires cke to be maintained ?high? for all valid operations as defined in this data sheet. if cke asynchronously drops ?low? during any valid operation dram is not guaranteed to preserve the contents of the memory array. if this event occurs, the memory controller must satisfy a time delay ( t delay ) before turn- ing off the clocks. stable clocks must exist at the input of dram before cke is raised ?high? again. the dram must be fully re-initialized as described the the initialization sequence starting with step 4. the dram is ready for normal operation after the initialization sequence. the minimum time clocks needs to be on after cke asynchronously drops low (the t delay timing parameter) is equal to tis + tck + tih. asynchronous cke low event cke cke drops low due to an asynchronous reset event clocks can be turned off after this point tdelay ck, ck stable clocks
55 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 truth tables func tion cke cs ras cas we ba0 ba1 a12-a11 a10 a9 - a0 notes previo us cycle curre nt cycle (extended) mode register set h h llllba op code 1, 2 auto-refresh hhlllhxxxx1 self-refresh entry hllllhxxxx1 self-refresh exit l h hxxxx x x x 1 lhhh x x 1 precharge all banks hhllhlxxhx1 bank activate h h l l h h ba row address 1, 2 write h h l h l l ba column l column 1,2,3 write with auto-precharge h h l h l l ba column h column 1,2,3 read h h l h l h ba column l column 1,2,3 read with auto-precharge hhlhlhbacolumnhcolumn1,2,3 no operation hxlhhhxxxx1 device deselect h x hxxxx x x x 1 power down entry hl hxxx xxxx1,4 lhhh power down exit lh hxxx xxxx1,4 lhhh 1. all ddr2 sdram commands are defined by states of c s , we, ra s, ca s, and cke at the rising edge of the clock. 2. bank addresses (ba0, ba1) determine which bank is to be operated upon. for (e)mrs ba selects an (extended) mode register. 3. burst reads or writes at bl = 4 cannot be terminated. see sections ?reads interrupted by a read? and ?writes inter- rupted by a write?. 4. the power down mode does not perform any refresh operations. the duration of power down is therefore limited by the refresh requirements. 5. the state of odt does not affect the states decribed in this table. the odt function is not available during self refresh. 6. ?x? means ?h or l (but a defined logic level)?. 7. operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the dram must be powered down and then restartet through the specified initialization sequence before normal operation can continue. command truth table xx single bank precharge hh llhl x l x ba 1, 2
56 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb clock enable (cke) truth table for synchronous transistions current state 2 cke command (n) 3,12 ras , cas , we , cs action (n) 3 notes previous cycle 1 (n-1) current cycle 1 (n) power-down ll x maintain power-down 13, 15 l h deselect or nop power-down exit 4, 8, 11 self refresh ll x maintain self refresh 15 l h deselect or nop self refresh exit 4, 5, 9 bank(s) active h l deselect or nop active power-down entry 4,8,10,11 all banks idle h l deselect or nop precharge power-down entry 4,8,10,11 h l autorefresh self refresh entry 6, 11 any state other than listed above hh refer to the command truth table 7 1. cke (n) is the logic state of cke at clock edge n; cke (n-1) was the state of cke at the previous clock edge. 2. current state is the state of the ddr2 sdram immediately prior to clock edge n. 3. command (n) is the command registered at clock edge n, and action (n) is a result of command (n). 4. all states and sequences not shown are illegal or reserved unless explicitely described elsewhere in this document. 5. on self refresh exit deselect or nop commands must be issued on every clock edge occuring during the txsnr period. read commands may be issued only after txsrd (200 clocks) is satisfied. 6. self refresh mode can only be entered from the all banks idle state. 7. must be a legal command as defined in the command truth table. 8. valid commands for power-down entry and exit are nop and deselect only. 9. valid commands for self refresh exit are nop and deselct only. 10. power-down and self refresh can not be entered while read or write operations, (extended) mode register operations, pre- charge or refresh operations are in progress. 11. minimum cke high time is 3 clocks, minimum cke low time is 3 clocks. 12. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 13. the power-down mode does not perform any refresh operations. the duration of power-down mode is therefor limited by the refresh requirements. 14. cke must be maintained high while the device is in ocd calibration mode, f.e. if any of the bits a7, a8, a9 in emrs are set to ?1?. 15. ?x? means ?don?t care (including floating around vref)? in self refresh and power down. however odt must be driven high or low in power down if the odt function is enabled (bit a2 or a6 set to ?1? in emrs). 16. operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the dram must be pow- ered down and then restartet through the specified initialization sequence before normal operation can continue. data mask (dm) truth table name (function) dm dqs notes write enable l valid 1 write inhibit h x 1 1. used to mask write data; provided coincident with the corresponding data.
57 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 absolute maximum dc ratings ac & dc operating conditions recommended dc operating conditions (sstl - 1.8) symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 1.0 v ~ 2.3 v v 1 vddq voltage on vddq pin relative to vss - 0.5 v ~ 2.3 v v 1 vddl voltage on vddl pin relative to vss - 0.5 v ~ 2.3 v v 1 v in , v out voltage on any pin relative to vss - 0.5 v ~ 2.3 v v 1 t stg storage temperature -55 to +100 c 1 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect r eli- ability. symbol parameter rating units notes min. typ. max. vdd supply voltage 1.7 1.8 1.9 v vddl supply voltage for dll 1.7 1.8 1.9 v 4 vddq supply voltage for output 1.7 1.8 1.9 v 4 vref input reference voltage 0.49*vddq 0.50*vddq 0.51*vddq v 1.2 vtt termination voltage v ref -0.04 v ref v ref +0.04 v 3 there is no specific device vdd supply voltage requirement for sstl-1.8 compliance. however under all conditions vddq must be less than or equal to vdd. 1. the value of vref may be selected by the user to provide optimum noise margin in the system. typically the value of vref is expected to be about 0.5 x vddq of the transmitting device and vref is expected to track variations in vddq. 2. peak to peak ac noise on vref may not exceed +/-2% vref (dc). 3. vtt of transmitting device must track vref of receiving device. 4. vddq tracks with vdd, vddl tracks with vdd. ac parameters are measured with vdd, vddq and vdddl tied together.
58 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb dc & ac logic input levels ddr2 sdram pin timing are specified for either single ended or differential mode depending on the setting of the emrs ?enable dqs ? mode bit; timing advantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timing are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at vref. in differen- tial mode, these timing relationships are measured relative to the crosspoint of dqs and its complement, dqs . this distinction in timing methods is guaranteed by design and characterisation. in single ended mode, the dqs (and rdqs ) signals are internally disabled and don?t care. single-ended dc input levels single-ended ac input test conditions symbol parameter min. max. uni ts vih (dc) dc input logic high vref + 0.125 vddq + 0.3 v vil (dc) dc input low - 0.3 vref - 0.125 v sym bol condi tion value uni ts notes vref input reference voltage 0.5 * vddq v 1 vswing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v / ns 2, 3 1. input waveform timing is referenced to the input signal crossing through the vref level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from vil(dc)max to vih(ac)min for ris- ing edges and the range from vih(dc)min to vil(ac)max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switching from vil(ac) to vih(ac) on the positive transitions and vih(ac) to vil(ac) on the negative transitions. v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss v swing(max) delta tr delta tf start of falling edge input timing start of rising edge input timing v ih(dc) min - v il(ac) max delta tf falling slew = rising slew = v ih(ac) min - v il(dc) max delta tr single-ended ac input levels symbol parameter ddr2 400,533 ddr2 667,800 units min max min max v ih (ac) ac input logic high vref+0.250 - vref+0.200 - v v il (ac) ac input logic low - vref-0.250 - vref-0.200 v
59 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 differential dc and ac input and output logic levels symbol parameter min. max. units notes v in(dc) dc input s ignal voltage -0.3 v ddq + 0.3 1 v id (dc) dc differential input volta ge 0.25 v d dq + 0.6 2 vid(ac) ac differential input voltage 0.5 vddq + 0.6 v 3 vix(ac) ac differential cross point input voltage 0.5 * vddq - 0.175 0.5 * vddq + 0.175 v 4 v o x (a c) ac differential cros s point output voltage 0.5 * v ddq - 0. 125 0. 5 * v ddq + 0. 125 v 5 notes : 1) v in(dc) s pecifies the allowable dc execution of each input of differential pair such as c k , c k , dqs , dqs ,etc. 2) v id (dc) s pecifies the input differential voltage v t r - v c p required for s witching. t he minimum value is equal to v ih( dc) - v il(dc). 3) v id (ac) s pecifies the input differential voltage v t r - v c p required for s witching. t he minimum value is equal to v ih( ac) - v il(ac). 4) the value of vix(ac) is expected to equal 0.5 x vddq of the transmitting device and vix(ac) is expected to track variations in v ddq. vix(ac) indicates the voltage at which differential input signals must cross. 5) the value of vox(ac) is expected to equal 0.5 x vddq of the transmitting device and vox(ac) is expected to track variations in vddq. vox(ac) indicates the voltage at which differential input signals must cross. crossing point vddq vssq vid vix or vox vtr vcp sstl18_3 parameter symbol ddr2-400 ddr2-533 ddr2-667 ddr2-800 units min max min max min max input capacitance, ck and ck cck 1.0 2.0 1.0 2.0 1.0 2.0 pf input capacitance delta, ck and ck cdck x 0.25 x 0.25 x 0.25 pf input capacitance, all other input-only pins ci 1.0 2.0 1.0 2.0 1.0 1.75 pf input capacitance delta, all other input-only pins cdi x 0.25 x 0.25 x 0.25 pf input/output capacitance, dq, dm, dqs, dqs cio 2.5 4.0 2.5 3.5 2.5 3.5 pf input/output capacitance delta, dq, dm, dqs, dqs cdio x 0.5 x 0.5 x 0.5 pf capacitance values
60 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb power and ground clamps are implemented on the following input only pins: 1. ba0-ba2 2. a0-a15 3. ras 4. cas 5. we 6. cs 7. odt 8. cke v-i characteristics for input only pins with clamps voltage across clamp(v) minimum power clamp current (ma) minimum ground clamp current (ma) 0.0 0 0 0.1 0 0 0.2 0 0 0.3 0 0 0.4 0 0 0.5 0 0 0.6 0 0 0.7 0 0 0.8 0.1 0.1 0.9 1.0 1.0 1.0 2.5 2.5 1.1 4.7 4.7 1.2 6.8 6.8 1.3 9.1 9.1 1.4 11.0 11.0 1.5 13.5 13.5 1.6 16.0 16.0 1.7 18.2 18.2 1.8 21.0 21.0
61 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 output ac test conditions output dc current drive ocd default characteristics notes: 1. absolute specifications (toper; vdd = +1.8v +/-0.1v, vddq = +1.8v +/-0.1v) 2. impedance measurement condition for output source dc current: vddq=1.7v; vout=1420mv; (vout-vddq)/ioh must be less than 23.4 ohms for values of vout between vddq and vddq-280mv. impedance measurement condition for output sink dc current: vddq = 1.7v; vout = 280mv; vout/iol must be less than 23.4 ohms for values of vout between 0v and 280mv. 3. mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage. 4. slew rate measured from vil(ac) to vih(ac). 5. the absolute value of the slew rate as measured from dc to dc is equal to or greater than the slew rate as measured from ac to ac. this is guaranteed by design and characterization. 6. this represents the step size when the ocd is near 18 ohms at nominal conditions across all process corners/variations and represents only the dram uncertainty. a 0 ohm value (no calibration) can only be achieved if the ocd impedance is 18 ohms +/- 0.75 ohms under nominal conditions. symbol parameter sstl_18 class ii units notes v oh minimum required output pull-up under ac test load v tt + 0.603 v v ol maximum required output pull-down under ac test load v tt - 0.603 v v otr output timing measurement reference level 0.5 * v ddq v1 1. the vddq of the device under test is referenced. symbol parameter sstl_18 class ii units notes i oh(dc) output minimum source dc current - 13.4 ma 1, 3, 4 i ol(dc) output minimum sink dc current 13.4 ma 2, 3, 4 1. v ddq = 1.7 v; v out = 1420 mv. (v out - v ddq )/i oh must be less than 21 ohm for values of v out between v ddq and v ddq - 280 mv. 2. v ddq = 1.7 v; v out = 280 mv. v out /i ol must be less than 21 ohm for values of v out between 0 v and 280 mv. 3. the dc value of v ref applied to the receiving device is set to v tt 4. the values of i oh(dc) and i ol(dc) are based on the conditions given in notes 1 and 2. they are used to test device drive current capability to ensure v ih min plus a noise margin and v il max minus a noise margin are delivered to an sstl_18 receiver. the actual current values are derived by shifting the desired driver operating point (see section 3.3) along a 21 ohm load line to define a convenient driver current for measurement. description parameter min nom max unit notes output impedance - - - 1 0 1.5 ohms 6 pull-up and pull-down mismatch 0 4 ohms 1,2,3 output impedance step size for ocd calibration output slew rate sout 1.5 - 5 v/ns 1,4,5,6,7,8 ohms
62 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb table 1. full strength default pu lldown driver characteristics figure 1. ddr2 default pulldown characte ristics for full strength driver pulldow n current (ma) voltage (v) minimum (23.4 ohms) nominal default low (18 ohms) nominal default high (18 ohms) maximum (12.6 ohms) 0.2 8.5 11.3 11.8 15.9 0.3 12.1 16.5 16.8 23.8 0.4 14.7 21.2 22.1 31.8 0.5 16.4 25.0 27.6 39.7 0.6 17.8 28.3 32.4 47.7 0.7 18.6 30.9 36.9 55.0 0.8 19.0 33.0 40.9 62.3 0.9 19.3 34.5 44.6 69.4 1.0 19.7 35.5 47.7 75.3 1.1 19.9 36.1 50.4 80.5 1.2 20.0 36.6 52.6 84.6 1.3 20.1 36.9 54.2 87.7 1.4 20.2 37.1 55.9 90.8 1.5 20.3 37.4 57.1 92.9 1.6 20.4 37.6 58.4 94.9 1.7 20.6 37.7 59.6 97.0 1.8 37.9 60.9 99.1 1.9 101.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 vout to vssq (v) 0 20 40 60 80 100 120 pulldown current (ma) maximum nominal default high nominal default low minimum
63 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 table 2. full strength default pullup driver characteristics figure 2. ddr2 default pullup characterist ics for full strength output driver pullup current (ma) voltage (v) minimum (23.4 ohms) nominal default low (18 ohms) nominal default high (18 ohms) maximum (12.6 ohms) 0.2 -8.5 -11.1 -11.8 -15.9 0.3 -12.1 -16.0 -17.0 -23.8 0.4 -14.7 -20.3 -22.2 -31.8 0.5 -16.4 -24.0 -27.5 -39.7 0.6 -17.8 -27.2 -32.4 -47.7 0.7 -18.6 -29.8 -36.9 -55.0 0.8 -19.0 -31.9 -40.8 -62.3 0.9 -19.3 -33.4 -44.5 -69.4 1.0 -19.7 -34.6 -47.7 -75.3 1.1 -19.9 -35.5 -50.4 -80.5 1.2 -20.0 -36.2 -52.5 -84.6 1.3 -20.1 -36.8 -54.2 -87.7 1.4 -20.2 -37.2 -55.9 -90.8 1.5 -20.3 -37.7 -57.1 -92.9 1.6 -20.4 -38.0 -58.4 -94.9 1.7 -20.6 -38.4 -59.6 -97.0 1.8 -38.6 -60.8 -99.1 1.9 -101.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 vddq to vout (v) -120 -100 -80 -60 -40 -20 0 pullup current (ma) minimum nominal default low nominal default high maximum
64 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb ddr2 sdram default output driver vCi characteristics ddr2 sdram output driver characte ristics are defined for full strength default operation as selected by the emrs1 bits a7-a9 = 111. figures 1 and 2 sh ow the driver characteristics graphically, and tables 1 and 2 show the same data in tabular format suitable for input into simulation to ols. the driver characteristics evaluation con ditions are: nominal default 25 o c (t case), vddq = 1.8 v, typical process minimum tbd o c (t case), vddq = 1.7 v, slowCslow process maximum 0 o c (t case), vddq = 1.9 v, fastCfast process default output driver characteristic curves notes: 1) the full variation in driver current from minimum to maximum process, tem perature, and voltage will lie within the outer bounding lines of the vCi curve of figures 1 and 2. 2) it is recommended tha t the typical ibis vCi curve lie within the inn er bounding lines of the vCi curves of figures 1 and 2. table 3. full strength calibrated pulldown driver characteristics table 4. full strength calibrated pullup driver characteristics ddr2 sdram calibrated output driver vCi characteristics ddr2 sdram output driver characte ristics are defined for full strength calibrated operation as selected by the procedure outlined in the section of off-chip driver (ocd) impedance adjustment. tables 3 and 4 show the data in tabular format suitabl e for input into simulation tools. the nominal points represent a device at exactly 18 ohms. the nominal low and nominal high values represent the range that can be achieved with a maximum 1.5 ohm step size with no calibration error at the exact nominal conditions only (i.e. perfect calibration procedure, 1.5 ohm maximum step size guaranteed by specification). real system calibration error needs to be added to these values. it must be understood tha t these v-i curves as repre- sented here or in supplier ibis models need to be adjusted to a wider range as a result of any system cali- bration error. since this is a system specific phenomena, it cannot be quantified here. the values in the calibrated tables represent just the dram po rtion of uncertainty wh ile looking at one dq only. if the cali - calibrated pulldow n current (ma) voltage (v) nominal minimum (21 ohms) nominal low (18.75 ohms) nominal (18 ohms) nominal high (17.2 ohms) nominal maximum (15 o hms) 0.2 9.5 10.7 11.5 11.8 13.3 0.3 14.3 16.0 16.6 17.4 20.0 0.4 18.7 21.0 21.6 23.0 27.0 calibrated pullup current (ma) voltage (v) nominal minimum (21 ohms) nominal (18 ohms) 0.2 -9.5 -10.7 -11.4 -11.8 -13.3 0.3 -14.3 -16.0 -16.5 -17.4 -20.0 0.4 -18.7 -21.0 -21.2 -23.0 -27.0 nominal low (18.75 ohms) nominal high (17.2 ohms) nominal maximum (15 o hms)
65 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 bration procedure is used, it is possible to cause the device to operate outside the bounds of the default device characteristics tables and figures. in such a situation, the timing parameters in the specification can- not be guaranteed. it is solely up to the system application to ensure that the device is calibrated between the minimum and maximum default values at all times. if this can?t be guaranteed by the system calibration pro- cedure, re-calibration policy, and uncertainty with dq to dq variation, then it is recommended that only the default values be used. the nominal maximum and minimum values represent the change in impedance from nominal low and high as a result of voltage and temperature change from the nominal condition to the maximum and minimum conditions. if calibrated at an extreme condition, the amount of variation could be as much as from the nominal minimum to the nominal maximum or vice versa. the driver characteristics evalu- ation conditions are: nominal 25 o c (t case), vddq = 1.8 v, typical process nominal low and nominal high 25 o c (t case), vddq = 1.8 v, any process nominal minimum tbd o c (t case), vddq = 1.7 v, any process nominal maximum 0 o c (t case), vddq = 1.9 v, any process
66 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb idd specifications and conditions ddr2-400/533/-667/-800 (0 deg c < tcase < 85 deg c; vddq=1.8v+ 0.1v; vdd=1.8v+ 0.1v) symbol parameter/condition i/o -5 ddr2-400 -3.7 ddr2-533 -3 ddr2-667 -25a/25 ddr2-800 unit notes i dd0 operating current x4/x8/ x16 80 110 80 115 90 120 100 132 ma 1,2 i dd1 operating current x4/x8/ x16 90 130 90 135 95 140 105 150 ma 1,2 i dd2p precharge power-down current x4/x8/ x16 8888 ma 1,2 i dd2n precharge standby current x4/x8/ x16 35 45 45 50 50 55 55 60 ma 1,2 i dd2q precharge quiet standby current x4/x8/ x16 30 40 40 45 45 50 50 55 ma 1,2 i dd3p active power down standby current mrs(12)=0 all 30 30 35 35 ma 1,2 active power down standby current mrs(12)=0 all 12 12 12 12 ma 1,2 i dd3n active standby current x4/x8/ x16 50 50 55 60 60 65 66 72 ma 1,2 i dd4r operating current burst read x4/x8/ x16 130 200 150 220 180 250 210 275 ma 1,2 i dd4w operating current burst read x4/x8/ x16 140 210 170 250 190 280 220 300 ma 1,2 i dd5b burst auto-refresh current (trfc=trfcmin) x4/x8/ x16 160 170 180 200 ma 1,2 i dd6 self-refresh current for standard products all 8 8 8 8 ma 1,2 i dd6 self-refresh current for low power products all 4 4 4 4 ma 1,2 i dd7 operating current x4/x8/ x16 220 330 220 335 220 340 270 350 ma 1,2
67 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 idd measurement cond itio ns (0 c < t case 85 c (tbd); vddq = 1.8v 0.1v; vdd = 1.8v 0.1v) symbol parameter/condition i dd0 operating current - one bank active - precharge trc = trcmin; tck =tckmin. ; databus inputs are switching; address and control inputs are switching, c s = high between valid commands. i dd1 operating c ur rent - one bank acti ve - read - precharg e one bank is accessed with trcmin , bl = 4, tck = tckmin, al = 0, cl = clmin.; address and control inputs are switching,c s = high between valid commands; l out = 0 ma. i dd2p precharg e power-do wn current: all banks idle; power-down mode; cke is low; tck = tckmin.; data bus inputs are floating. i dd2n precharge standby current: all banks idle; c s is high; cke is high; tck = tckmin.; address and control inputs are switching; data bus inputs are switching. . i dd2q precharge quiet standby current: all banks idle; c s is high; cke is high; tck = tckmin.; address and control inputs are stable; data bus inputs are floating. i dd3p ac ti ve power-do wn current: all banks open; cke is low; address and control inputs are stable; data bus inputs are floating. mrs a12 bit is set to ?0?( fast power-down exit); i dd3p ac ti ve power-do wn current: all banks open; cke is low; address and control inputs are stable; data bus inputs are floating. mrs a12 bit is set to ?1?( slow power-down exit); i dd3n act ive standby current: all banks open; c s is high; cke is high; trc = trasmax; tck = tckmin.; address and control inputs are switching; data bus inputs are switching. i dd4r operating curre nt - burs t read: all banks active; continuous burst reads; bl = 4;al = 0, cl = clmin.; tck = tckmin.; address and control inputs are switching; data bus inputs are switching; iout = 0ma. i dd4w operating curre nt - burs t write: all banks active; continuous burst writes; bl = 4;al = 0, cl = clmin.; tck = tckmin.; address and control inputs are switching; data bus inputs are switching; iout = 0ma. i dd5b burs t au to -refresh current: refresh command at trfc = trfcmin, tck = tckmin, c s is high between valid commands i dd5d distri buted au to-refresh current: refresh command at trefi; tck = tckmin, c s is high between valid commands; cke is low except during trfcmin. i dd6 self-refresh current: cke 0.2v; external clock off, ck and c k at 0v; tck = tckmin; address and control inputs are floating; data bus inputs are floating. i dd7 operating bank interleave read current: 1. all bank interleaving with bl = 4; bl = 4, cl = clmin.;trcd = trcdmin.; trrd = trrdmin.;al = trcd - 1, iout = 0 ma. address and control inputs are stable during deselect; data bus inputs are switching. 2. timing pattern: - ddr2 -400 (200mhz, cl=3) : tck = 5 ns, bl = 4, trcd = 3 * tck, al = 2 * tck, trc = 12 * tck read : a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d d d - ddr2 -533 (266mhz, cl=4) : tck = 3.7 ns, bl = 4, trcd = 4 * tck, al = 3 * tck, trc = 16 * tck read : a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d - ddr2 -667 (333mhz, cl=4) : tck = 3 ns, bl = 4, trcd = 4 * tck, al = 3 * tck, trc = 19 * tck read : a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d 1. data bus consists of dq, dm, dqs, dq s, rdqs, rdq s, ldqs, ldq s, udqs and udq s. 2. definitions for idd : low is defined as vin <= vilac(max.); high is defined as vin >= vihac(min.); stable is defined as inputs are stable at a high or low level floating is defined as inputs are vref switching is defined as inputs are changing between high and low every other clock for adress and control sign als, and inputs changing 50% of each data trasnfer for dq signals. 3. legend : a=activate, ra=read with auto-precharge, d=deselect _ _ <
68 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb ac characteristics (ac operating conditions unless otherwise noted) parameter symbol (ddr2-400) -5 (ddr2-533) -37 (ddr2-667) -3 (ddr2-800) -25a (ddr2-800) -25 unit note min max min max min max min max min max row cycle time t rc 55 - 60 - 60 - 60 - 57.25 - ns auto refresh row cycle time t rfc 105 - 105 - 105 - 105 - 105 - ns 11 row active time t ras 40 70k 45 70k 45 70k 45 70k 45 70k ns 21 row address to column address delay t rcd 15 - 15 - 15 - 15 - 12.5 - ns 20 row active to row active delay (x4 & x8) t rrd 7.5 - 7.5 - 7.5 - 7.5 - 7.5 - ns row active to row active delay (x16) t rrd 10 - 10 - 10 - 10 - 10 - ns column address to column address delay t ccd 2 - 2 - 2 - 2 - 2 - clk row precharge time t rp 15 - 15 - 15 - 15 - 12.5 - ns write recovery time t wr 15 - 15 - 15 - 15 - 15 - ns last data-in to read command t drl 1 - 1 - 1 - 1 - 1 - clk auto precharge write recovery + precharge time t dal t wr +t rp - t wr +t rp - t wr +t rp - t wr +t rp - t wr +t rp - ns 12 system clock cycle time cas latency = 3 t ck 5858585858ns2 cas latency = 4 5 8 3.75 8 3.75 8 3.75 8 3.75 8 ns 2 cas latency = 5 583.75838382.58ns2 cas latency = 6 5 8 3.75 8 3 8 2.5 8 2.5 8 ns clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 clk clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 clk data-out edge to clock edge skew t ac -0.60 0.60 -0.50 0.50 -0.45 0.45 -0.40 0.40 -0.40 0.40 ns dqs-out edge to clock edge skew t dqsck -0.50 0.50 -0.45 0.45 -0.40 0.40 -0.35 0.35 -0.35 0.35 ns dqs-out edge to data-out edge skew t dqsq - 0.35 - 0.30 - 0.24 - 0.20 - 0.20 ns data-out hold time from dqs t qh t hpmin -t qhs - t hpmin -t qhs - t hpmin -t qhs - t hpmin -t qhs - t hpmin -t qhs - ns data hold skew factor t qhs - 450 - 400 - 340 - 300 - 300 ps clock half period t hp t ch/l min - t ch/l min - t ch/l min - t ch/l min - t ch/l min - ns 5 input setup time (fast slew rate) t is 350 - 250 - 200 - 175 - 175 - ps 15,17 input hold time (fast slew rate) t ih 475 - 375 - 275 - 250 - 250 - ps 15,17 input pulse width t ipw 0.6 - 0.6 - 0.6 - 0.6 - 0.6 - clk
69 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 write dqs high level width t dqsh 0.35 0.35 0.35 0.35 0.35 clk write dqs low level width t dqsl 0.35 0.35 0.35 0.35 0.35 clk clk to first rising edge of dqs-in t dqss wl- 0.25t ck wl+ 0.25t ck wl- 0.25t ck wl+ 0.25t ck wl- 0.25t ck wl+ 0.25t ck wl- 0.25t ck wl+ 0.25t ck wl- 0.25t ck wl+ 0.25t ck clk data-in setup time to dqs-in (dq & dm) t ds 150 - 100 - 50 - 50 - 50 - ps 16,17, 18 data-in hold time to dqs-in (dq & dm) t dh 275 - 225 - 175 - 125 - 125 - ps 16,17, 18 dqs falling edge to clk rising setup time t dss 0.2 - 0.2 - 0.2 - 0.2 - 0.2 - clk dqs falling edge from clk rising hold time t dsh 0.2 - 0.2 - 0.2 - 0.2 - 0.2 - clk dq & dm input pulse width t dipw 0.35 - 0.35 - 0.35 - 0.35 - 0.35 - clk read dqs preamble time t rpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 clk read dqs postamble time t rpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 clk write dqs preamble setup time t wpres 0 - 0 - 0 - 0 - 0 - clk write dqs preamble hold time t wpreh 0.25 - 0.25 - 0.25 - 0.25 - 0.25 - clk write dqs postamble time t wpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 clk 10 internal read to precharge command delay t rtp 7.5 - 7.5 - 7.5 - 7.5 - 7.5 - ns internal write to read command delay t wtr 10 - 7.5 - 7.5 - 7.5 - 7.5 - ns 13 data out high impedance time from clk/clk t hz t ac(min) t ac(max) t ac(min) t ac(max) t ac(min) t ac(max) t ac(min) t ac(max) t ac(min) t ac(max) ns 7 data out low impedance time from clk/clk t lz t ac(min) t ac(max) t ac(min) t ac(max) t ac(min) t ac(max) t ac(min) t ac(max) t ac(min) t ac(max) ns 7 mode register set delay t mrd 2- 2- 2- 2- 2- clk9 exit self refresh to non-read com- mand t xsnr t rfc +10 - t rfc +10 - t rfc +10 - t rfc +10 - t rfc +10 - ns 19 exit self refresh to read command t xsrd 200 - 200 - 200 - 200 - 200 - clk exit precharge power down to any non-read command t xp 2 - 2 - 2- 2- 2- clk14 exit active power down to read com- mand t xard 2- 2- 2- 2- 2- clk exit active power down to read com- mand (slow exit, lower power) t xards 6-al - 6-al - 6-al - 6-al - 6-al - clk odt drive mode output delay t oit 012012012012012ns minimum time clocks remains on af- ter cke asynchronously drops low t delay tis+tck +tih tis+tck +tih tis+tck +tih tis+tck +tih tis+tck +tih ns parameter symbol (ddr2-400) -5 (ddr2-533) -37 (ddr2-667) -3 (ddr2-800) -25a (ddr2-800) -25 unit note min max min max min max min max min max
70 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb cke minimum high and low pulse width t cke 3 - 3 - 3 - 3 - 3 - clk average periodic refresh interval 0c < t < 85c t refi - 7.8 - 7.8 - 7.8 - 7.8 - 7.8 us 18 parameter symbol (ddr2-400) -5 (ddr2-533) -37 (ddr2-667) -3 (ddr2-800) -25a (ddr2-800) -25 unit note min max min max min max min max min max
71 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 notes for electrical characteristics & ac timing 1. input slew rate is 1 v/ns and ac timings are guarantedd for linear signal transitions. for other slew rates see the derating tables on the next pages. 2. the ck / ck input reference level (for timing reference to ck / ck) is the point at which ck and ck cross:the dqs / dqs input reference level is the crosspoint when in differential strobe mode; the input reference level for signals other than ck/ ck , or dqs / dqs is vref . 3. inputs are not recognized as valid until vref stabilizes. during the period before vref stabilizes, cke = 0.2 x vddq is recognized as low. 4. the output timing reference voltage level is vtt. 5. min (tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tcl and tch. 6. for input frequency change during dram operation. 7. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are no t referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 8. these parameters guarantee device timing, but they are not necessarily tested on each device. 9. the specific requirement is that dqs and dq s be valid (high, low, or some point on a valid transition) on or befor e this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device . when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previ - ous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending o n t dqss . when programmed in differential strobe mode, dqs is always the logic complement of dqs except when both are in high-z. 1 0. the maximum limit for this parameter is not a device limit. the device operate with a greater value for this paramete r, but system performance (bus turnaround) degrades accordingly. 11. a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. (note : trfc depends on dram density) 1 2. for each of the terms, if not allready an integer, round to the next highest integer. tck refers to the application cloc k period. wr refers to the wr parameter stored in the mrs. 1 3. twtr is at least two clocks independent of operation frequency. 1 4. user can choose two different active power-down modes for additional power saving via mrs address bit a12. in ?standard active power-down mode? (mrs, a12 = ?0?) a fast power-down exit timing txard can be used. in ?low active power-down mode? (mrs, a12 =?1?) a slow power-down exit timing txards has to be satisfied. 1 5. timings are guaranteed with command / address input slew rate of 1.0 v/ns. 1 6. timings are guaranteed with data / mask input slew rate of 1.0 v/ns. 1 7. timings are guaranteed with ck /c k differential slew rate 2.0 v/ns, and dqs/dq s ( and rdqs/ rdqs) differential slew rate 2.0 v/ns in differential strobe mode. 1 8. if refresh timing or tds / tdh is violated, data corruption may occur and the data must be re-written with valid data before a valid read can be executed. 1 9. in all circumstances, txsnr can be satisfied using txsnr = trfc + 10 ns. 2 0. the trcd timing parameter is valid for both activate command to read or write command with and without auto-pr e- charge. therefore a separate parameter trap for activate command to read or write command with auto-precharg e is not neccessary anymore. 2 1. tras(max) is calculated from the maximum amount of time a ddr2 device can operate without a refresh comman d which is equal to 9 * trefi.
72 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb reference loads, slew rates and slew rate derating reference load for timing measurements the figure represents the timing reference load used in defining the relevant timing parameters of the device. it is not intended to either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. system designers will use ibis or other simulation tools to cor- relate the timing reference load to a system environment. this load circuit is also used for output slew rate measurements. 25 ohm vtt = vddq / 2 ck, ck dut timing reference points vddq dq dqs dqs rdqs rdqs note: the output timing reference voltage level for single ended signals is the crosspoint with vtt. the output timing reference voltage level for differential signals is the crosspoint of the true (e.g. dqs) and the complement (e.g. dqs ) signal. slew rate measurements output slew rate output slew rate is characterized under the test conditions as shown in the figure below 25 ohm vtt = vddq / 2 dut test point vddq dq dqs rdqs output slew rate for falling and rising edges is measured between vtt - 250 mv and vtt + 250 mv for single ended signals.for differential signals (e.g. dqs - dqs ) output slew rate is measured between dqs - dqs = - 500 mv and dqs - dqs = + 500 mv.output slew rate is guaranteed by design, but is not necessarilty tested on each device. input slew rate input slew for single ended signals is measured from dc-level to ac-level from vref - 125 mv to verf + 250 mv for rising edges and from vref + 125 mv to vref - 250 mv for falling edges. for differential signals (e.g. ck - ck ) slew rate for rising edges is measured from ck - ck = -250 mv to ck -ck = +500 mv (250 mv to -500 mv for falling edges). test conditions are the same as for timing mea- surements.
73 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 overshoot and undershoot specification ac overshoot / undershoot specification for address and control pins ac overshoot / undershoot specification for clock, data, strobe and mask pins parameter ddr2 -400 ddr2 -533 ddr2 -667 units maximum peak amplitude allowed for overshoot area 0.9 0.9 0.9 v maximum peak amplitude allowed for undershoot area 0.9 0.9 0.9 v maximum overshoot area above vdd 0.75 0.56 0.45 v.ns maximum undershoot area below vss 0.75 0.56 0.45 v.ns parameter ddr2 -400 ddr2 -533 ddr2 -667 units maximum peak amplitude allowed for overshoot area 0.9 0.9 0.9 v maximum peak amplitude allowed for undershoot area 0.9 0.9 0.9 v maximum overshoot area above vddq 0.38 0.28 0.23 v.ns maximum undershoot area below vssq 0.38 0.28 0.23 v.ns vdd vss overshoot area undershoot area maximum amplitude maximum amplitude time (ns) volts (v) vddq vssq overshoot area undershoot area maximum amplitude maximum amplitude time (ns) volts (v)
74 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb package dimension (x4/x8) 60ball fine pitch ball grid array outline
75 promos technologies v59c1512(404/804/164)qb v59c1512(404/804/164)qb rev. 1.3 november 2006 package dimension (x16) 84ball fine pitch ball grid array outline
76 v59c1512(404/804/164)qb rev. 1.3 november 2006 promos technologies v59c1512(404/804/164)qb worldwide offices ? copyright ,promos technology. printed in u.s.a. the information in this document is subject to change without notice. promos tech makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of promos tech. promos tech subjects its products to normal quality cont rol sampling techniques which are intended to provide an assura nc of high quality products suitable for usual commercial app lica tions. promos tech does not do testing appropriate to prov ide 100% product quality assurance and does not assume any li ab ity for consequential or incidental arising from any use of its p rod ucts. if such products are to be used in applications in w hic personal injury might occur from failure, purchaser must d oi own quality assurance testing appropriate to such application s. taiwan(taipei) 7f, no. 102 min-chuan e. road sec. 3, taipei, taiwan, r.o.c phone: 886-2-2545-1213 fax: 886-2-2545-1209 no. 19 li hsin road science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-566-3952 fax: 886-3-578-6028 japan onze 1852 building 6f 2-14-6 shintomi, chuo-ku tokyo 104-0041 phone: 81-3-3537-1400 fax: 81-3-3537-1402 usa(west) 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 sales offices: taiwan(hsinchu) usa(east) 25 creekside road hopewell jct, ny 12533 phone:845-223-1689 fax:845-223-1684

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